diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-03-23 19:24:53 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-05-09 08:46:42 +0200 |
| commit | bf48fbbcc116b79fa5bfe05db83c354ee87e3843 (patch) | |
| tree | ec259ca22f496383fad4ab8a18a265c09c64b838 /src/soc/rockchip/rk3399/include | |
| parent | 08d177b091be4758c7b541a5f9550b849e6dd092 (diff) | |
| download | coreboot-bf48fbbcc116b79fa5bfe05db83c354ee87e3843.tar.xz | |
rockchip: rk3399: support saradc
This patch add functions to configure saradc clk and get
saradc's raw value for each channel.
Currently add saradc to ramstage.
Please refer to TRM V0.3 Part 2 Chapter 18 for this IP.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=on kevin board, get the raw value 61 for channel 0,
measure the ADC_IN0 as 0.109V,
61.0/1024 = 0.05957 0.109V/1.8V = 0.06056
Change-Id: Ic198b2a964ccf8bb687441f0e2702665402fff6e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc400316de2d75eccad3990a4187bf2dc49a844a
Original-Change-Id: I542430ed97bd27f9bfcec89b1d703d9fa390d4e0
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/334177
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14720
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/rk3399/include')
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/clock.h | 1 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/saradc.h | 21 |
2 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index ff4edb57ff..4e96e997a8 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -105,6 +105,7 @@ enum apll_l_frequencies { void rkclk_init(void); void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq); void rkclk_configure_ddr(unsigned int hz); +void rkclk_configure_saradc(unsigned int hz); void rkclk_configure_spi(unsigned int bus, unsigned int hz); void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); uint32_t rkclk_i2c_clock_for_bus(unsigned bus); diff --git a/src/soc/rockchip/rk3399/include/soc/saradc.h b/src/soc/rockchip/rk3399/include/soc/saradc.h new file mode 100644 index 0000000000..90f743e9f6 --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/saradc.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __SOC_ROCKCHIP_RK3399_SARADC_H__ +#define __SOC_ROCKCHIP_RK3399_SARADC_H__ + +u32 get_saradc_value(u32 chn); +#endif |