diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-04-08 18:56:20 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-05-18 20:23:18 +0200 |
| commit | 2f7ed8d775153db69d19c77cc79db9b0bb136c70 (patch) | |
| tree | 774f21bf49a9f5486c9242e9124d1db48e9eaf04 /src/soc/rockchip/rk3399/include | |
| parent | 95b7a6c6db47bd493a11fa14aa949ddb6788e8db (diff) | |
| download | coreboot-2f7ed8d775153db69d19c77cc79db9b0bb136c70.tar.xz | |
rockchip: rk3399: configure emmc clk
Select aclk_emmc and clk_emmc source from GPLL, and both to 198MHz,
that is GPLL(594MHz) divided by 3.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=boot kevin rev1 to chromeos prompt from both emmc and sdcard
TEST=LoadKernel faster, more than twice as I measured manually.
Change-Id: I2580c43b8c79049c3fe16bbf60bfa1a8e0559948
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: 5fd37b66dcce77354e1cafab0d6e806d832c08d2
Original-Change-Id: Id22815b302af3204e0e5537af99c1577b09b0877
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/339152
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14855
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Diffstat (limited to 'src/soc/rockchip/rk3399/include')
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/clock.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 3b60d547cf..286abec06f 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -106,6 +106,7 @@ void rkclk_init(void); int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz); void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq); void rkclk_configure_ddr(unsigned int hz); +void rkclk_configure_emmc(void); void rkclk_configure_saradc(unsigned int hz); void rkclk_configure_spi(unsigned int bus, unsigned int hz); void rkclk_configure_tsadc(unsigned int hz); |