diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-02 22:03:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-04 14:11:17 +0000 |
| commit | 55009af42c39f413c49503670ce9bc2858974962 (patch) | |
| tree | 099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/rockchip/rk3399/saradc.c | |
| parent | 1c371572188a90ea16275460dd4ab6bf9966350b (diff) | |
| download | coreboot-55009af42c39f413c49503670ce9bc2858974962.tar.xz | |
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/rockchip/rk3399/saradc.c')
| -rw-r--r-- | src/soc/rockchip/rk3399/saradc.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/rockchip/rk3399/saradc.c b/src/soc/rockchip/rk3399/saradc.c index 3c6cbe648f..358bb6a7e0 100644 --- a/src/soc/rockchip/rk3399/saradc.c +++ b/src/soc/rockchip/rk3399/saradc.c @@ -60,15 +60,15 @@ u32 get_saradc_value(u32 chn) rkclk_configure_saradc(SARADC_HZ); /* power down adc converter */ - clrbits_le32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); + clrbits32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); /* select channel */ - clrsetbits_le32(&rk3399_saradc->ctrl, - ADC_CHN_SEL_MASK << ADC_CHN_SEL_SHIFT, - chn << ADC_CHN_SEL_SHIFT); + clrsetbits32(&rk3399_saradc->ctrl, + ADC_CHN_SEL_MASK << ADC_CHN_SEL_SHIFT, + chn << ADC_CHN_SEL_SHIFT); /* power up */ - setbits_le32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); + setbits32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); udelay(SARADC_DELAY_PU); |