diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-02 22:03:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-04 14:11:17 +0000 |
| commit | 55009af42c39f413c49503670ce9bc2858974962 (patch) | |
| tree | 099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/rockchip/rk3399/tsadc.c | |
| parent | 1c371572188a90ea16275460dd4ab6bf9966350b (diff) | |
| download | coreboot-55009af42c39f413c49503670ce9bc2858974962.tar.xz | |
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/rockchip/rk3399/tsadc.c')
| -rw-r--r-- | src/soc/rockchip/rk3399/tsadc.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c index 7ec24648a2..78ce1e366e 100644 --- a/src/soc/rockchip/rk3399/tsadc.c +++ b/src/soc/rockchip/rk3399/tsadc.c @@ -100,7 +100,7 @@ void tsadc_init(uint32_t polarity) rkclk_configure_tsadc(TSADC_CLOCK_HZ); /* tsadc power sequence */ - clrbits_le32(&rk3399_tsadc->user_con, ADC_POWER_CTRL); + clrbits32(&rk3399_tsadc->user_con, ADC_POWER_CTRL); write32(&rk3399_grf->tsadc_testbit_l, GRF_TSADC_TSEN_PD0_ON); udelay(50); write32(&rk3399_grf->tsadc_testbit_l, GRF_TSADC_TSEN_PD0_OFF); @@ -125,9 +125,9 @@ void tsadc_init(uint32_t polarity) write32(&rk3399_tsadc->auto_period_ht, AUTO_PERIOD_HT); write32(&rk3399_tsadc->hight_tshut_debounce, AUTO_DEBOUNCE_HT); /* Enable the src0, negative temprature coefficient */ - setbits_le32(&rk3399_tsadc->auto_con, Q_SEL | SRC0_EN); + setbits32(&rk3399_tsadc->auto_con, Q_SEL | SRC0_EN); udelay(100); - setbits_le32(&rk3399_tsadc->auto_con, AUTO_EN); + setbits32(&rk3399_tsadc->auto_con, AUTO_EN); write32(&rk3399_tsadc->comp0_shut, TSADC_SHUT_VALUE); write32(&rk3399_tsadc->int_en, TSHUT_CRU_EN_SRC0 | TSHUT_GPIO_EN_SRC0); |