diff options
| author | Patrick Georgi <pgeorgi@google.com> | 2016-11-02 11:36:07 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2016-12-03 00:17:00 +0100 |
| commit | e6407161f3c853f24afbb0ab82e327f0396f57ac (patch) | |
| tree | bb90083ec61855412b51a6411c02e87679ac395c /src/soc/rockchip/rk3399 | |
| parent | b1feb5189b2e8955a9b945e6dfc8e92eb044b66c (diff) | |
| download | coreboot-e6407161f3c853f24afbb0ab82e327f0396f57ac.tar.xz | |
rockchip/rk3399: Fix typo
TRAINING, not TARINING.
BUG=none
BRANCH=none
TEST=still builds
Change-Id: I8b7ffd0f0544a58865865a8b09d9c153db9c2674
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b1ea846ce1ffd654d7d34c2a1d43b0fddbd4ae32
Original-Change-Id: I4940279ed7217cc20fe29c8b3603d1853acbfc5e
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/411801
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17677
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/rockchip/rk3399')
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/sdram.h | 2 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/sdram.c | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/sdram.h b/src/soc/rockchip/rk3399/include/soc/sdram.h index bf99b35f36..6fdb7076e5 100644 --- a/src/soc/rockchip/rk3399/include/soc/sdram.h +++ b/src/soc/rockchip/rk3399/include/soc/sdram.h @@ -190,7 +190,7 @@ struct rk3399_sdram_params { #define PI_READ_GATE_TRAINING (1 << 2) #define PI_READ_LEVELING (1 << 3) #define PI_WDQ_LEVELING (1 << 4) -#define PI_FULL_TARINING (0xff) +#define PI_FULL_TRAINING (0xff) void sdram_init(const struct rk3399_sdram_params *sdram_params); u32 sdram_get_ram_code(void); diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 4ea31dde1f..d085e4c44e 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -637,7 +637,7 @@ static int data_training(u32 channel, /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ setbits_le32(&denali_phy[927], (1 << 22)); - if (training_flag == PI_FULL_TARINING) { + if (training_flag == PI_FULL_TRAINING) { if (sdram_params->dramtype == LPDDR4) { training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | PI_READ_GATE_TRAINING | @@ -972,7 +972,7 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params) for (channel = 0; channel < ch_count; channel++) { denali_phy = rk3399_ddr_publ[channel]->denali_phy; clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); - if (data_training(channel, sdram_params, PI_FULL_TARINING)) { + if (data_training(channel, sdram_params, PI_FULL_TRAINING)) { printk(BIOS_ERR, "index1 training failed, reset\n"); hard_reset(); } @@ -1014,7 +1014,7 @@ void sdram_init(const struct rk3399_sdram_params *sdram_params) if (dramtype == LPDDR3) udelay(10); - if (data_training(channel, sdram_params, PI_FULL_TARINING)) { + if (data_training(channel, sdram_params, PI_FULL_TRAINING)) { printk(BIOS_ERR, "SDRAM initialization failed, reset\n"); hard_reset(); |