diff options
author | Lin Huang <hl@rock-chips.com> | 2016-09-15 22:59:55 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2016-11-02 17:29:48 +0100 |
commit | 883f5cbdcea6e8e4dbca57ff0a430338c9159ed2 (patch) | |
tree | 5fb86a9b3dcc8537c240c81ebafd275897fe9948 /src/soc/rockchip/rk3399 | |
parent | 84164603188175abd2a3d8eeab1adc5efc33330f (diff) | |
download | coreboot-883f5cbdcea6e8e4dbca57ff0a430338c9159ed2.tar.xz |
rockchip/rk3399: sdram: also prepare the index1 configuration
To enable DDR Dynamic Voltage and Frequency Scaling (DVFS) we need to
train alternative configurations first, so do the training and store the
values.
BUG=None
BRANCH=None
TEST=Boot from kevin
Change-Id: I944a4b297a4ed6966893aa09553da88171307a42
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 94533ff3ba21bcb0ace00bedcf0cebb89a341be2
Original-Change-Id: I4a98bc0db5553d154fedb657e35b926a92aa80c7
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/386596
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17104
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/rockchip/rk3399')
-rw-r--r-- | src/soc/rockchip/rk3399/include/soc/addressmap.h | 2 | ||||
-rw-r--r-- | src/soc/rockchip/rk3399/include/soc/sdram.h | 12 | ||||
-rw-r--r-- | src/soc/rockchip/rk3399/sdram.c | 32 |
3 files changed, 45 insertions, 1 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h index d316c3805d..1762a8d277 100644 --- a/src/soc/rockchip/rk3399/include/soc/addressmap.h +++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h @@ -17,7 +17,6 @@ #define __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__ #define MAX_DRAM_ADDRESS 0xF8000000 - #define PMUGRF_BASE 0xff320000 #define PMUSGRF_BASE 0xff330000 #define PMUCRU_BASE 0xff750000 @@ -69,6 +68,7 @@ #define SERVER_MSCH0_BASE_ADDR 0xffa84000 #define DDRC1_BASE_ADDR 0xffa88000 #define SERVER_MSCH1_BASE_ADDR 0xffa8c000 +#define CIC_BASE_ADDR 0xff620000 #define USB_OTG0_DWC3_BASE 0xfe80c100 #define USB_OTG1_DWC3_BASE 0xfe90c100 diff --git a/src/soc/rockchip/rk3399/include/soc/sdram.h b/src/soc/rockchip/rk3399/include/soc/sdram.h index 1ec6d3958c..bf99b35f36 100644 --- a/src/soc/rockchip/rk3399/include/soc/sdram.h +++ b/src/soc/rockchip/rk3399/include/soc/sdram.h @@ -127,6 +127,18 @@ struct rk3399_msch_timings { u32 agingx0; }; +struct rk3399_ddr_cic_regs { + u32 cic_ctrl0; + u32 cic_ctrl1; + u32 cic_idle_th; + u32 cic_cg_wait_th; + u32 cic_status0; + u32 cic_status1; + u32 cic_ctrl2; + u32 cic_ctrl3; + u32 cic_ctrl4; +}; + /* DENALI_CTL_00 */ #define START (1) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index ee980339a1..688bdeb589 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -41,6 +41,7 @@ static struct rk3399_ddr_publ_regs * const rk3399_ddr_publ[2] = { (void *)DDRC0_PHY_BASE_ADDR, (void *)DDRC1_PHY_BASE_ADDR }; static struct rk3399_msch_regs * const rk3399_msch[2] = { (void *)SERVER_MSCH0_BASE_ADDR, (void *)SERVER_MSCH1_BASE_ADDR }; +static struct rk3399_ddr_cic_regs *const rk3399_ddr_cic = (void *)CIC_BASE_ADDR; /* * sys_reg bitfield struct @@ -725,6 +726,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } + clrbits_le32(&denali_pi[100], 0x3 << 8); } /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ @@ -771,6 +773,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } + clrbits_le32(&denali_pi[60], 0x3 << 8); } /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ @@ -817,6 +820,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } + clrbits_le32(&denali_pi[80], 0x3 << 24); } /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ @@ -849,6 +853,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } + clrbits_le32(&denali_pi[80], 0x3 << 16); } /* wdq leveling(LPDDR4 support) */ @@ -880,6 +885,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } + clrbits_le32(&denali_pi[124], 0x3 << 16); } /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ @@ -971,6 +977,30 @@ static void dram_all_config(const struct rk3399_sdram_params *sdram_params) clrsetbits_le32(&cru_ptr->glb_rst_con, 0x3, 0x3); } +static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params) +{ + u32 channel; + u32 *denali_phy; + u32 ch_count = sdram_params->num_channels; + + write32(&rk3399_ddr_cic->cic_ctrl0, + RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1, + 1 << 4 | 1 << 2 | 1)); + while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 2))) + ; + + write32(&rk3399_ddr_cic->cic_ctrl0, RK_CLRSETBITS(1 << 1, 1 << 1)); + while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 0))) + ; + + for (channel = 0; channel < ch_count; channel++) { + denali_phy = rk3399_ddr_publ[channel]->denali_phy; + clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); + if (data_training(channel, sdram_params, PI_FULL_TARINING)) + printk(BIOS_DEBUG, "training failed\n"); + } +} + void sdram_init(const struct rk3399_sdram_params *sdram_params) { unsigned char dramtype = sdram_params->dramtype; @@ -1016,6 +1046,8 @@ void sdram_init(const struct rk3399_sdram_params *sdram_params) sdram_params->ch[channel].ddrconfig); } dram_all_config(sdram_params); + switch_to_phy_index1(sdram_params); + printk(BIOS_INFO, "Finish SDRAM initialization...\n"); } |