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authorMarty E. Plummer <hanetzer@startmail.com>2019-04-20 01:38:51 -0500
committerJulius Werner <jwerner@chromium.org>2019-04-30 22:38:10 +0000
commit22e605c2c06f553b98131a87b634709aa1818e1f (patch)
treeb5d0f2f66b65e7ce4e7e4eadc2d81e59252fe97c /src/soc/rockchip/rk3399
parent6672bd8e6b808300a98be0ce308a2bfe5b4685d6 (diff)
downloadcoreboot-22e605c2c06f553b98131a87b634709aa1818e1f.tar.xz
rockchip: rk3399: increase memory for fit payload.
Increase ramstage to 2M, required to actually embed the 7.2mb uImage into the coreboot.rom, increase the postram cbfs cache in order for the fit image to be loadable (without this increase the fit payload is found but not loaded) Change-Id: Iee0ed9f7958588ceda54bb32253c84cac68abea2 Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/rockchip/rk3399')
-rw-r--r--src/soc/rockchip/rk3399/include/soc/memlayout.ld4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index 73fc499d1c..293057a091 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -20,8 +20,8 @@ SECTIONS
{
DRAM_START(0x00000000)
BL31(0, 0x100000)
- POSTRAM_CBFS_CACHE(0x00100000, 1M)
- RAMSTAGE(0x00300000, 256K)
+ POSTRAM_CBFS_CACHE(0x00100000, 8M)
+ RAMSTAGE(0x00900000, 2M)
DMA_COHERENT(0x10000000, 2M)
/* 8K of special SRAM in PMU power domain. */