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authorJulius Werner <jwerner@chromium.org>2017-04-12 13:38:56 -0700
committerMartin Roth <martinroth@google.com>2017-05-24 16:30:39 +0200
commit34dba35831f8c46ea96a9049737b4a367b1b6460 (patch)
tree633f6fdf0131a08f764475b7ed24865b70c7776b /src/soc/rockchip/rk3399
parentb25b2329a9e03d1b019f989f0073ac7ef518fb38 (diff)
downloadcoreboot-34dba35831f8c46ea96a9049737b4a367b1b6460.tar.xz
rk3399: Reshuffle memlayout to move PRERAM_CBMEM_CONSOLE further back
It seems that the BootROM on the RK3399 overwrites some of the earlier parts of SRAM, including the PRERAM_CBMEM_CONSOLE area. Now that we have a persistent CBMEM console we want that area to survive in case of an early (pre-CBMEM) reboot, so shuffle the layout around a bit to move it further back. (This reduces the stack size to 12KB which should still be way more than enough.) Change-Id: Ifc1e568cda334394134bba9eba75088032d2ff13 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/rockchip/rk3399')
-rw-r--r--src/soc/rockchip/rk3399/include/soc/memlayout.ld12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index f440dfb391..04ffce66ce 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -29,13 +29,13 @@ SECTIONS
SYMBOL(epmu_sram, 0xFF3B2000)
SRAM_START(0xFF8C0000)
- PRERAM_CBMEM_CONSOLE(0xFF8C0000, 7K)
+ PRERAM_CBFS_CACHE(0xFF8C0000, 7K)
TIMESTAMP(0xFF8C1C00, 1K)
BOOTBLOCK(0xFF8C2004, 36K - 4)
- PRERAM_CBFS_CACHE(0xFF8CB000, 4K)
- OVERLAP_VERSTAGE_ROMSTAGE(0xFF8CC000, 92K)
- VBOOT2_WORK(0XFF8E3000, 12K)
- TTB(0xFF8E6000, 24K)
- STACK(0xFF8EC000, 16K)
+ OVERLAP_VERSTAGE_ROMSTAGE(0xFF8CB000, 92K)
+ VBOOT2_WORK(0XFF8E2000, 12K)
+ TTB(0xFF8E5000, 24K)
+ PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K)
+ STACK(0xFF8ED000, 12K)
SRAM_END(0xFF8F0000)
}