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authorElyes HAOUAS <ehaouas@noos.fr>2018-11-26 22:53:49 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-11-29 12:17:45 +0000
commit6df3b64c77a868ab8526b980561ed2be3fe392b6 (patch)
treea95ac78c1e4e222971ee9749e9e114494681e9c4 /src/soc/rockchip
parent1a5ce95815210032783d01e830390ee5b6a54dc5 (diff)
downloadcoreboot-6df3b64c77a868ab8526b980561ed2be3fe392b6.tar.xz
src: Remove duplicated round up function
This removes CEIL_DIV and div_round_up() altogether and replace it by DIV_ROUND_UP defined in commonlib/helpers.h. Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/rockchip')
-rw-r--r--src/soc/rockchip/common/i2c.c2
-rw-r--r--src/soc/rockchip/common/rk808.c8
-rw-r--r--src/soc/rockchip/rk3288/clock.c8
-rw-r--r--src/soc/rockchip/rk3288/sdram.c12
-rw-r--r--src/soc/rockchip/rk3399/clock.c12
-rw-r--r--src/soc/rockchip/rk3399/mipi.c10
6 files changed, 26 insertions, 26 deletions
diff --git a/src/soc/rockchip/common/i2c.c b/src/soc/rockchip/common/i2c.c
index f99b3b57ce..8629a70580 100644
--- a/src/soc/rockchip/common/i2c.c
+++ b/src/soc/rockchip/common/i2c.c
@@ -280,7 +280,7 @@ void i2c_init(unsigned int bus, unsigned int hz)
/* SCL Divisor = 8*(CLKDIVL + 1 + CLKDIVH + 1)
SCL = PCLK / SCLK Divisor */
- clk_div = div_round_up(i2c_src_clk, hz * 8);
+ clk_div = DIV_ROUND_UP(i2c_src_clk, hz * 8);
divh = clk_div * 3 / 7 - 1;
divl = clk_div - divh - 2;
i2c_clk = i2c_src_clk / (8 * (divl + 1 + divh + 1));
diff --git a/src/soc/rockchip/common/rk808.c b/src/soc/rockchip/common/rk808.c
index 9b4708cfab..58d910c285 100644
--- a/src/soc/rockchip/common/rk808.c
+++ b/src/soc/rockchip/common/rk808.c
@@ -92,13 +92,13 @@ void rk808_configure_ldo(int ldo, int millivolts)
case 4:
case 5:
case 8:
- vsel = div_round_up(millivolts, 100) - 18;
+ vsel = DIV_ROUND_UP(millivolts, 100) - 18;
assert(vsel <= 0x10);
break;
case 3:
case 6:
case 7:
- vsel = div_round_up(millivolts, 100) - 8;
+ vsel = DIV_ROUND_UP(millivolts, 100) - 8;
assert(vsel <= 0x11);
break;
default:
@@ -118,12 +118,12 @@ void rk808_configure_buck(int buck, int millivolts)
case 1:
case 2:
/* 25mV steps. base = 29 * 25mV = 725 */
- vsel = (div_round_up(millivolts, 25) - 29) * 2 + 1;
+ vsel = (DIV_ROUND_UP(millivolts, 25) - 29) * 2 + 1;
assert(vsel <= 0x3f);
buck_reg = BUCK1SEL + 4 * (buck - 1);
break;
case 4:
- vsel = div_round_up(millivolts, 100) - 18;
+ vsel = DIV_ROUND_UP(millivolts, 100) - 18;
assert(vsel <= 0xf);
buck_reg = BUCK4SEL;
break;
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index 1b1c135d98..28c7a426d4 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -519,15 +519,15 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div, u32 *ext_div)
return -1;
}
- no = div_round_up(VCO_MIN_KHZ, freq_khz);
+ no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
if (ext_div) {
- *ext_div = div_round_up(no, max_no);
- no = div_round_up(no, *ext_div);
+ *ext_div = DIV_ROUND_UP(no, max_no);
+ no = DIV_ROUND_UP(no, *ext_div);
}
/* only even divisors (and 1) are supported */
if (no > 1)
- no = div_round_up(no, 2) * 2;
+ no = DIV_ROUND_UP(no, 2) * 2;
vco_khz = freq_khz * no;
if (ext_div)
diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c
index ad5661e1c4..4149a4721d 100644
--- a/src/soc/rockchip/rk3288/sdram.c
+++ b/src/soc/rockchip/rk3288/sdram.c
@@ -644,7 +644,7 @@ static void pctl_cfg(u32 channel,
static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params)
{
u32 i;
- u32 dinit2 = div_round_up(sdram_params->ddr_freq/MHz * 200000, 1000);
+ u32 dinit2 = DIV_ROUND_UP(sdram_params->ddr_freq/MHz * 200000, 1000);
struct rk3288_ddr_publ_regs *ddr_publ_regs = rk3288_ddr_publ[channel];
struct rk3288_msch_regs *msch_regs = rk3288_msch[channel];
@@ -658,14 +658,14 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params)
write32(&msch_regs->devtodev,
BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1));
write32(&ddr_publ_regs->ptr[0],
- PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq / MHz * 5120, 1000))
- | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq / MHz * 50, 1000))
+ PRT_DLLLOCK(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 5120, 1000))
+ | PRT_DLLSRST(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 50, 1000))
| PRT_ITMSRST(8));
write32(&ddr_publ_regs->ptr[1],
- PRT_DINIT0(div_round_up(sdram_params->ddr_freq / MHz * 500000, 1000))
- | PRT_DINIT1(div_round_up(sdram_params->ddr_freq / MHz * 400, 1000)));
+ PRT_DINIT0(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 500000, 1000))
+ | PRT_DINIT1(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 400, 1000)));
write32(&ddr_publ_regs->ptr[2], PRT_DINIT2(MIN(dinit2, 0x1ffff))
- | PRT_DINIT3(div_round_up(sdram_params->ddr_freq / MHz * 1000, 1000)));
+ | PRT_DINIT3(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 1000, 1000)));
switch (sdram_params->dramtype) {
case LPDDR3:
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 0b8c83f90e..cce1d69ee6 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -429,10 +429,10 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
return -1;
}
- postdiv1 = div_round_up(VCO_MIN_KHZ, freq_khz);
+ postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
if (postdiv1 > max_postdiv1) {
- postdiv2 = div_round_up(postdiv1, max_postdiv1);
- postdiv1 = div_round_up(postdiv1, postdiv2);
+ postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
+ postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
}
vco_khz = freq_khz * postdiv1 * postdiv2;
@@ -605,9 +605,9 @@ void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster)
apll_hz = apll_cfgs[freq]->freq;
rkclk_set_pll(pll_con, apll_cfgs[freq]);
- aclkm_div = div_round_up(apll_hz, ACLKM_CORE_HZ) - 1;
- pclk_dbg_div = div_round_up(apll_hz, PCLK_DBG_HZ) - 1;
- atclk_div = div_round_up(apll_hz, ATCLK_CORE_HZ) - 1;
+ aclkm_div = DIV_ROUND_UP(apll_hz, ACLKM_CORE_HZ) - 1;
+ pclk_dbg_div = DIV_ROUND_UP(apll_hz, PCLK_DBG_HZ) - 1;
+ atclk_div = DIV_ROUND_UP(apll_hz, ATCLK_CORE_HZ) - 1;
write32(&cru_ptr->clksel_con[con_base],
RK_CLRSETBITS(ACLKM_CORE_DIV_CON_MASK <<
diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c
index 813746e01e..114b202d1b 100644
--- a/src/soc/rockchip/rk3399/mipi.c
+++ b/src/soc/rockchip/rk3399/mipi.c
@@ -45,7 +45,7 @@ static void rk_mipi_dsi_wait_for_two_frames(struct rk_mipi_dsi *dsi,
int two_frames;
unsigned int refresh = edid->mode.refresh;
- two_frames = div_round_up(MSECS_PER_SEC * 2, refresh);
+ two_frames = DIV_ROUND_UP(MSECS_PER_SEC * 2, refresh);
mdelay(two_frames);
}
@@ -158,7 +158,7 @@ static int rk_mipi_dsi_wait_phy_lock(struct rk_mipi_dsi *dsi)
static int rk_mipi_dsi_phy_init(struct rk_mipi_dsi *dsi)
{
int i, vco, val;
- int lane_mbps = div_round_up(dsi->lane_bps, USECS_PER_SEC);
+ int lane_mbps = DIV_ROUND_UP(dsi->lane_bps, USECS_PER_SEC);
struct stopwatch sw;
vco = (lane_mbps < 200) ? 0 : (lane_mbps + 100) / 200;
@@ -318,7 +318,7 @@ static int rk_mipi_dsi_get_lane_bps(struct rk_mipi_dsi *dsi,
fref = OSC_HZ;
/* constraint: 5Mhz <= Fref / N <= 40MHz */
- min_prediv = div_round_up(fref, 40 * MHz);
+ min_prediv = DIV_ROUND_UP(fref, 40 * MHz);
max_prediv = fref / (5 * MHz);
/* constraint: 80MHz <= Fvco <= 1500Mhz */
@@ -441,7 +441,7 @@ static u32 rk_mipi_dsi_get_hcomponent_lbcc(struct rk_mipi_dsi *dsi,
u64 lbcc_tmp;
lbcc_tmp = hcomponent * dsi->lane_bps / (8 * MSECS_PER_SEC);
- lbcc = div_round_up(lbcc_tmp, edid->mode.pixel_clock);
+ lbcc = DIV_ROUND_UP(lbcc_tmp, edid->mode.pixel_clock);
return lbcc;
}
@@ -532,7 +532,7 @@ static void rk_mipi_dsi_init(struct rk_mipi_dsi *dsi)
* which is:
* (lane_mbps >> 3) / 20 > esc_clk_division
*/
- u32 esc_clk_division = div_round_up(dsi->lane_bps,
+ u32 esc_clk_division = DIV_ROUND_UP(dsi->lane_bps,
8 * 20 * USECS_PER_SEC);
write32(&dsi->mipi_regs->dsi_pwr_up, RESET);