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| author | Vadim Bendebury <vbendeb@chromium.org> | 2016-05-22 16:09:54 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-08 23:21:55 +0200 |
| commit | 9ed93cb5d50f94f9c43db2eb29764cd6302b4bb0 (patch) | |
| tree | 0dc76c952e9ed6269d28bf1ead9666ee6d4f2534 /src/soc/rockchip | |
| parent | 221fdd8cce708f192a457f39a703e9a968b2f847 (diff) | |
| download | coreboot-9ed93cb5d50f94f9c43db2eb29764cd6302b4bb0.tar.xz | |
gru: kevin: configure board GPIOs
Set board GPIOs as required and add their description into the
appropriate section of the coreboot table, to make them available to
depthcharge.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to use
keyboard on Gru, which indicates that the EC interrupt GPIO is
properly configured. The rest of the pins will be verified later.
Change-Id: I5818bfe855f4e7faa2114484a9b7b44c7d469727
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: e02a05f
Original-Change-Id: I82be76bbd3211179e696526a34cc842cb1987e69
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346631
Reviewed-on: https://review.coreboot.org/15031
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/rockchip')
| -rw-r--r-- | src/soc/rockchip/rk3399/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 8abafe362b..77958d577f 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -47,6 +47,8 @@ romstage-y += ../common/pwm.c romstage-y += timer.c romstage-y += romstage.c romstage-y += tsadc.c +romstage-y += gpio.c +romstage-y += ../common/gpio.c ################################################################################ |