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author | Deepti Deshatty <deepti.deshatty@intel.com> | 2021-05-12 16:34:21 +0530 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-14 08:58:07 +0000 |
commit | bfa60433cb6afa824c60dd166947b229af366fdc (patch) | |
tree | ac3ddd100a9401cda755a1ad125988b5af2b4a1a /src/soc/rockchip | |
parent | 8386e7cd5bf763c281c0b25e6de127c289766de5 (diff) | |
download | coreboot-bfa60433cb6afa824c60dd166947b229af366fdc.tar.xz |
soc/intel/alderlake: Add known GPIO virtual wire information
GPIO communities 0, 1, and 4 have virtual wire indexes & bits for at
least some of their groups; add the known information into the community
definitions. This patch is ported form tigerlake.
Change-Id: I2f1e2413d06e8afe4233d7111763cb45b78f845b
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/rockchip')
0 files changed, 0 insertions, 0 deletions