diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-19 21:45:57 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-21 16:18:49 +0000 |
| commit | b6265139c7b0e1dfc1706ba896349e59d62a069d (patch) | |
| tree | e14bb669bdccad83475d6ccd2d85664d4b252226 /src/soc/rockchip | |
| parent | 0c2724c844d0923b70b634abcad54a8ad04ef9e8 (diff) | |
| download | coreboot-b6265139c7b0e1dfc1706ba896349e59d62a069d.tar.xz | |
soc/rockchip: Drop unneeded empty lines
Change-Id: I6932580a373608d3d2fa5d844efdc7ffbc577d1f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/soc/rockchip')
| -rw-r--r-- | src/soc/rockchip/common/edp.c | 1 | ||||
| -rw-r--r-- | src/soc/rockchip/common/include/soc/edp.h | 1 | ||||
| -rw-r--r-- | src/soc/rockchip/common/include/soc/spi.h | 1 | ||||
| -rw-r--r-- | src/soc/rockchip/common/pwm.c | 1 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/include/soc/hdmi.h | 1 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/addressmap.h | 1 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/sdram.c | 1 |
7 files changed, 0 insertions, 7 deletions
diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index 627603fae5..422b306a14 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -280,7 +280,6 @@ static int rk_edp_dpcd_write(struct rk_edp *edp, u32 addr, return rk_edp_dpcd_transfer(edp, addr, values, size, DPCD_WRITE); } - static int rk_edp_link_power_up(struct rk_edp *edp) { u8 value; diff --git a/src/soc/rockchip/common/include/soc/edp.h b/src/soc/rockchip/common/include/soc/edp.h index cd5c543381..702d99f843 100644 --- a/src/soc/rockchip/common/include/soc/edp.h +++ b/src/soc/rockchip/common/include/soc/edp.h @@ -523,7 +523,6 @@ check_member(rk_edp_regs, pll_reg_5, 0xa00); #define EDID_HEADER 0x00 #define EDID_EXTENSION_FLAG 0x7e - enum dpcd_request { DPCD_READ, DPCD_WRITE, diff --git a/src/soc/rockchip/common/include/soc/spi.h b/src/soc/rockchip/common/include/soc/spi.h index 0184fefa6d..dfaf42629f 100644 --- a/src/soc/rockchip/common/include/soc/spi.h +++ b/src/soc/rockchip/common/include/soc/spi.h @@ -32,7 +32,6 @@ struct rockchip_spi { }; check_member(rockchip_spi, rxdr, 0x800); - #define SF_READ_DATA_CMD 0x3 /* --------Bit fields in CTRLR0--------begin */ diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index d1e980addf..bb09700b36 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -25,7 +25,6 @@ check_member(rk_pwm_regs, int_en, 0x44); #define RK_PWM_DISABLE (0 << 0) #define RK_PWM_ENABLE (1 << 0) - #define PWM_ONE_SHOT (0 << 1) #define PWM_CONTINUOUS (1 << 1) #define RK_PWM_CAPTURE (1 << 2) diff --git a/src/soc/rockchip/rk3288/include/soc/hdmi.h b/src/soc/rockchip/rk3288/include/soc/hdmi.h index 93ef9cb2ed..0f49722df9 100644 --- a/src/soc/rockchip/rk3288/include/soc/hdmi.h +++ b/src/soc/rockchip/rk3288/include/soc/hdmi.h @@ -263,7 +263,6 @@ enum { HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, - /* fc_aviconf0-fc_aviconf3 field values */ HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h index 06fd781d8e..bf69aecd56 100644 --- a/src/soc/rockchip/rk3399/include/soc/addressmap.h +++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h @@ -52,7 +52,6 @@ #define VOP_BIG_BASE 0xff900000 /* corresponds to vop_id 0 */ #define VOP_LIT_BASE 0xff8f0000 /* corresponds to vop_id 1 */ - #define DDRC0_BASE_ADDR 0xffa80000 #define SERVER_MSCH0_BASE_ADDR 0xffa84000 #define DDRC1_BASE_ADDR 0xffa88000 diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index bc89c37af3..fc7499f2d8 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -434,7 +434,6 @@ static void phy_io_config(u32 channel, /* PHY_939 PHY_PAD_CS_DRIVE */ clrsetbits32(&denali_phy[939], 0x7 << 14, mode_sel << 14); - /* speed setting */ if (sdram_params->ddr_freq < 400 * MHz) speed = 0x0; |