rockchip/rk3399: Set all 4 DVFS voltage rails to 1.1V @300kHz

Previous code had several problems:
* It was only initting 3 of the 4 voltage rails hooked up to PWM
  regulators.
* It was using a PWM frequency that was out of range.  Apparently from
  testing 300kHz is best.
* It was initting all rails to .9V.  On my Kevin I needed 1.1V to make
  booting all 6 cores / rebooting reliable.

With this fix both booting all 6 cores in the kernel is reliable (if we
tell the kernel not to touch the PWM) and the "reboot" command from
Linux userspace is also reliable (previously it crashed in coreboot).

NOTES:
* Setting all rails to the same voltage doesn't make a lot of sense.  We
  should figure out what these should _actually_ be.  Presumably the
  little CPU rail can be lower, at least.  ...and we don't use the GPU
  in the BIOS so we should set that lower.

BRANCH=none
BUG=chrome-os-partner:51922
TEST=reboot test

Change-Id: I44f6394e43d291cccf3795ad73ee5b21bd949766
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ac79a7cfb079d23c9d7c4899fdf18c87d05ed0e
Original-Change-Id: I80996adefd8542d53ecce59e5233c553700b309f
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/339151
Reviewed-on: https://review.coreboot.org/14727
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 43 insertions, 1 deletions

diff --git a/src/soc/rockchip/rk3399/romstage.c b/src/soc/rockchip/rk3399/romstage.c
index 05c853eb84..f22b8c9116 100644
--- a/src/soc/rockchip/rk3399/romstage.c
+++ b/src/soc/rockchip/rk3399/romstage.c
@@ -24,19 +24,61 @@
 #include <delay.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
-#include <symbols.h>
 #include <soc/addressmap.h>
+#include <soc/grf.h>
 #include <soc/mmu_operations.h>
+#include <soc/pwm.h>
 #include <soc/sdram.h>
+#include <symbols.h>
 
 static const uint64_t dram_size =
 	(uint64_t)min((uint64_t)CONFIG_DRAM_SIZE_MB * MiB, MAX_DRAM_ADDRESS);
 
+static void init_dvs_outputs(void)
+{
+	uint32_t i;
+
+	write32(&rk3399_grf->iomux_pwm_0, IOMUX_PWM_0);		/* GPU */
+	write32(&rk3399_grf->iomux_pwm_1, IOMUX_PWM_1);		/* Big */
+	write32(&rk3399_pmugrf->iomux_pwm_2, IOMUX_PWM_2);	/* Little */
+	write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A);	/* Centerlog */
+
+	/*
+	 * Notes:
+	 *
+	 * design_min = 0.8
+	 * design_max = 1.5
+	 *
+	 * period = 3333     # 300 kHz
+	 * volt = 1.1
+	 *
+	 * # Intentionally round down (higher volt) to be safe.
+	 * int((period / (design_max - design_min)) * (design_max - volt))
+	 *
+	 * Tested on kevin rev0 board 82 w/ all 4 PWMs:
+	 *
+	 *   period = 3333, volt = 1.1: 1904 -- Worked for me!
+	 *   period = 3333, volt = 1.0: 2380 -- Bad
+	 *   period = 3333, volt = 0.9: 2856 -- Bad
+	 *
+	 *   period = 25000, volt = 1.1: 14285 -- Bad
+	 *   period = 25000, volt = 1.0: 17857 -- Bad
+	 *
+	 * TODO: Almost certainly we don't need all 4 PWMs set to the same
+	 * thing.  We should experiment
+	 */
+	for (i = 0; i < 4; i++)
+		pwm_init(i, 3333, 1904);
+}
+
 void main(void)
 {
 	console_init();
 	exception_init();
 
+	/* Init DVS to conservative values. */
+	init_dvs_outputs();
+
 	sdram_init(get_sdram_config());
 
 	mmu_config_range((void *)0, (uintptr_t)dram_size, CACHED_MEM);