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authorArthur Heymans <arthur@aheymans.xyz>2019-10-20 01:00:57 +0200
committerArthur Heymans <arthur@aheymans.xyz>2019-11-03 11:19:04 +0000
commit2f389f151a0db244def706bc90fd17fe091d8537 (patch)
tree4269a24bc3f25749c85eb39357d68135964e35ef /src/soc/rockchip
parent7c9a0e8a9cfa90f8f413f3b485f8103bca80fac6 (diff)
downloadcoreboot-2f389f151a0db244def706bc90fd17fe091d8537.tar.xz
arch/arm: Pass cbmem_top to ramstage via calling argument
This solution is very generic and can in principle be implemented on all arch/soc. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. Mechanisms set in place to pass on information from rom- to ram-stage will be placed in a followup commit. Change-Id: If31f0f1de17ffc92c9397f32b26db25aff4b7cab Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/rockchip')
-rw-r--r--src/soc/rockchip/rk3288/Makefile.inc2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index 7e4c5b48ad..e7982f7492 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -18,7 +18,6 @@ ifeq ($(CONFIG_SOC_ROCKCHIP_RK3288),y)
IDBTOOL = util/rockchip/make_idb.py
bootblock-y += bootblock.c
-bootblock-y += ../common/cbmem.c
bootblock-y += ../common/uart.c
bootblock-y += timer.c
bootblock-y += clock.c
@@ -55,7 +54,6 @@ romstage-y += tsadc.c
romstage-y += ../common/i2c.c
ramstage-y += soc.c
-ramstage-y += ../common/cbmem.c
ramstage-y += timer.c
ramstage-y += ../common/i2c.c
ramstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c