diff options
| author | Yunzhi Li <lyz@rock-chips.com> | 2015-06-19 17:09:04 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-06 09:40:02 +0200 |
| commit | aa33609d289c4ee07ec10e4825bc055492fa107c (patch) | |
| tree | 1ef5470236076ecd703ec52dd1a33a00c1fc88f7 /src/soc/rockchip | |
| parent | 394933640bc0515617117ed0cb8de7702bc9c1bf (diff) | |
| download | coreboot-aa33609d289c4ee07ec10e4825bc055492fa107c.tar.xz | |
libpayload: usb: dwc2: support interrupt transfer
dwc2 host core do not have a periodic schedule list, so try to send
an interrupt packet in poll_intr_queue() function and use frame
number read from usb core register to calculate time and schedule
transfers.
BUG=None
TEST=Tested on RK3288 with two USB keyboards(connect to SoC without
USB hub), both work correctly.
BRANCH=None
Change-Id: I16f7977c45a84b37c32b7c495ca78ad76be9f0ce
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d0206b86634bcfdbe03da3e2c8adf186470e157
Original-Change-Id: Ie54699162ef799f4d3d2a0abf850dbeb62417777
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/280750
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10774
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip')
0 files changed, 0 insertions, 0 deletions