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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-09-01 16:08:02 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-08 05:24:42 +0000 |
| commit | 62669a24eaf5236a60eebf8e26eefc984ca321ee (patch) | |
| tree | d28d15f4e71cd3fb481aa4f73438460c4e49031a /src/soc/rockchip | |
| parent | 7f844ab8b710e3244d1e681e800d99163cc9c65f (diff) | |
| download | coreboot-62669a24eaf5236a60eebf8e26eefc984ca321ee.tar.xz | |
cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK
The IA32_SMRR_PHYS_MASK MSR contains a 'Lock' bit, which will cause the
core to generate a #GP if the SMRR_BASE or SMRR_MASK registers are
written to after the Lock bit is set; this is helpful with securing SMM.
BUG=b:164489598
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I784d1d1abec0a0fe0ee267118d084ac594a51647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/rockchip')
0 files changed, 0 insertions, 0 deletions