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| author | Jacob Garber <jgarber1@ualberta.ca> | 2019-07-23 11:55:04 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-07-25 16:03:53 +0000 |
| commit | e24585c834598720cd925592ffd80af6e9f74f83 (patch) | |
| tree | 5660f33d43fe76a889c6658a52521377feb700f5 /src/soc/rockchip | |
| parent | 17887d08fee6d10bc4ff8758694b88435365e5d7 (diff) | |
| download | coreboot-e24585c834598720cd925592ffd80af6e9f74f83.tar.xz | |
soc/rockchip/rk3399: Use 64 bits in multiplication
This multiplication is of the form u64 = u32 * u32. Despite being stored
in a 64 bit variable, the intermediate value is still calculated using
32 bit math, which could possibly overflow. Cast one of the variables to
a u64 to ensure it uses 64 bit math instead to avoid this.
Change-Id: Ib08624812e933fdca5a51150ab36d3be49383326
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1375443
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/rockchip')
| -rw-r--r-- | src/soc/rockchip/rk3399/mipi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index 1f3f02cbee..8b80bd724b 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -305,7 +305,7 @@ static int rk_mipi_dsi_get_lane_bps(struct rk_mipi_dsi *dsi, dsi->format); return bpp; } - pclk = edid->mode.pixel_clock * MSECS_PER_SEC; + pclk = (u64)edid->mode.pixel_clock * MSECS_PER_SEC; /* take 1 / 0.8, since mbps must bigger than bandwidth of RGB */ target_bps = pclk / panel_data->lanes * bpp / 8 * 10; |