diff options
| author | Julius Werner <jwerner@chromium.org> | 2016-08-15 17:58:05 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-20 00:32:13 +0200 |
| commit | 1c8491c3ab75cc54c5288552b3ffb8513a3488aa (patch) | |
| tree | dafce8770f91809093bd9597e257d26d1bb8804f /src/soc/rockchip | |
| parent | a2d4062d427d18127707306dada5e79d69bd3691 (diff) | |
| download | coreboot-1c8491c3ab75cc54c5288552b3ffb8513a3488aa.tar.xz | |
gru: Add USB 2.0 PHY tuning for Kevin
This patch sets some magic number in magic undocumented registers that
are rumored to make USB 2.0 signal integrity better on Kevin. I don't
see any difference (unfortunately it doesn't solve the problems with
long cables on my board), but I guess it doesn't hurt either way.
BRANCH=None
BUG=chrome-os-partner:56108,chrome-os-partner:54788
TEST=Booted Kevin with USB connected through Servo. Seems to have
roughly the same failure rate as before.
Change-Id: If31fb49f1ed7218b50f24e251e54c9400db72720
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0c5c8f0f80ea1ebb042bcb91506a6100833e7e84
Original-Change-Id: Ifbd47bf6adb63a2ca5371c0b05c5ec27a0fe3195
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/370900
Original-Reviewed-by: Guenter Roeck <groeck@chromium.org>
Original-Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-on: https://review.coreboot.org/16265
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/rockchip')
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/grf.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/grf.h b/src/soc/rockchip/rk3399/include/soc/grf.h index d76b827b89..c1fd690e78 100644 --- a/src/soc/rockchip/rk3399/include/soc/grf.h +++ b/src/soc/rockchip/rk3399/include/soc/grf.h @@ -73,7 +73,7 @@ struct rk3399_grf_regs { u32 reserved11[3]; u32 usbphy0_ctrl[26]; u32 reserved12[6]; - u32 usbphy1[26]; + u32 usbphy1_ctrl[26]; u32 reserved13[0x72f]; u32 soc_con9; u32 reserved14[0x0a]; |