rockchip/rk3399: mipi: correct phy parameter setting

As MIPI PHY document show, icpctrl<3..0> and lpfctrl<5..0>
should depend on frequency, so fix it.

Change-Id: Ic4a90767bd1f22d5d784d4013dc7afb3149115c1
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

2 files changed, 76 insertions, 31 deletions

diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h
index bccaf287d3..077e05ef42 100644
--- a/src/soc/rockchip/rk3399/include/soc/mipi.h
+++ b/src/soc/rockchip/rk3399/include/soc/mipi.h
@@ -186,10 +186,23 @@ check_member(rk_mipi_regs, dsi_int_msk1, 0xc8);
 #define VCO_IN_CAP_CON_HIGH	(0x2 << 1)
 #define REF_BIAS_CUR_SEL	BIT(0)
 
-#define CP_CURRENT_3MA		BIT(3)
+#define CP_CURRENT_1_5UA	0x0
+#define CP_CURRENT_3UA		0x1
+#define CP_CURRENT_4_5UA	0x2
+#define CP_CURRENT_7_5UA	0x6
+#define CP_CURRENT_6UA		0x9
+#define CP_CURRENT_12UA		0xb
+#define CP_CURRENT_SEL(val)	((val) & 0xf)
+
 #define CP_PROGRAM_EN		BIT(7)
+
 #define LPF_PROGRAM_EN		BIT(6)
-#define LPF_RESISTORS_20_KOHM	0
+#define LPF_RESISTORS_15_5KOHM	0x1
+#define LPF_RESISTORS_13KOHM	0x2
+#define LPF_RESISTORS_11_5KOHM	0x4
+#define LPF_RESISTORS_10_5KOHM	0x8
+#define LPF_RESISTORS_8KOHM	0x10
+#define LPF_RESISTORS_SEL(val)	((val) & 0x3f)
 
 #define HSFREQRANGE_SEL(val)	(((val) & 0x3f) << 1)
 
@@ -271,9 +284,11 @@ enum {
 	MIPI_DCS_SET_DISPLAY_ON = 0x29,
 };
 
-struct dphy_pll_testdin_map {
+struct dphy_pll_parameter_map {
 	unsigned int max_mbps;
-	u8 testdin;
+	u8 hsfreqrange;
+	u8 icpctrl;
+	u8 lpfctrl;
 };
 
 struct rk_mipi_dsi {
diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c
index 9491b91d7f..f44c7993ca 100644
--- a/src/soc/rockchip/rk3399/mipi.c
+++ b/src/soc/rockchip/rk3399/mipi.c
@@ -47,26 +47,56 @@ static void rk_mipi_dsi_wait_for_two_frames(struct rk_mipi_dsi *dsi,
 	mdelay(two_frames);
 }
 
-static const struct dphy_pll_testdin_map dptdin_map[] = {
-	{  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
-	{ 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
-	{ 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
-	{ 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
-	{ 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
-	{ 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
-	{ 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
-	{1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
-	{1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
-	{1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
+static const struct dphy_pll_parameter_map dppa_map[] = {
+	{  89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM},
+	{  99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM},
+	{ 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM},
+	{ 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
+	{ 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
+	{ 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
+	{ 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},
+	{ 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},
+	{ 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},
+	{ 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},
+	{ 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},
+	{ 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},
+	{ 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM},
+	{ 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM},
+	{ 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
+	{ 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
+	{ 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
+	{ 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+	{ 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+	{ 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM},
+	{ 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM},
+	{ 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+	{ 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+	{ 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+	{ 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+	{ 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+	{ 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+	{ 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
+	{ 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
+	{1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
+	{1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
+	{1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+	{1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+	{1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+	{1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+	{1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+	{1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+	{1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+	{1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM}
 };
 
-static int max_mbps_to_testdin(unsigned int max_mbps)
+static int max_mbps_to_parameter(unsigned int max_mbps)
 {
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
-		if (dptdin_map[i].max_mbps > max_mbps)
-			return dptdin_map[i].testdin;
+	for (i = 0; i < ARRAY_SIZE(dppa_map); i++) {
+		if (dppa_map[i].max_mbps >= max_mbps)
+			return i;
+	}
 
 	return -1;
 }
@@ -95,16 +125,16 @@ static void rk_mipi_dsi_phy_write(struct rk_mipi_dsi *dsi,
 
 static int rk_mipi_dsi_phy_init(struct rk_mipi_dsi *dsi)
 {
-	int testdin, vco;
-
+	int i, vco;
 	int lane_mbps = div_round_up(dsi->lane_bps, USECS_PER_SEC);
+
 	vco = (lane_mbps < 200) ? 0 : (lane_mbps + 100) / 200;
 
-	testdin = max_mbps_to_testdin(lane_mbps);
-	if (testdin < 0) {
-		printk(BIOS_DEBUG, "failed to get testdin for %dmbps\n",
-		       lane_mbps);
-		return testdin;
+	i = max_mbps_to_parameter(lane_mbps);
+	if (i < 0) {
+		printk(BIOS_DEBUG,
+		       "failed to get parameter for %dmbps clock\n", lane_mbps);
+		return i;
 	}
 
 	/* Start by clearing PHY state */
@@ -119,14 +149,14 @@ static int rk_mipi_dsi_phy_init(struct rk_mipi_dsi *dsi)
 			      REF_BIAS_CUR_SEL);
 
 	rk_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
-			      CP_CURRENT_3MA);
+			      CP_CURRENT_SEL(dppa_map[i].icpctrl));
 	rk_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
 			      CP_PROGRAM_EN |
 			      LPF_PROGRAM_EN |
-			      LPF_RESISTORS_20_KOHM);
-
+			      LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
 	rk_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
-			      HSFREQRANGE_SEL(testdin));
+			      HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
+
 	rk_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
 			      INPUT_DIVIDER(dsi->input_div));
 	rk_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
@@ -182,7 +212,7 @@ static int rk_mipi_dsi_get_lane_bps(struct rk_mipi_dsi *dsi,
 	u32 i, pre;
 	u64 pclk, pllref, tmp, target_bps;
 	u32 m = 1, n = 1;
-	u32 max_bps = 1500 * MHz;
+	u32 max_bps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps * MHz;
 	int bpp;
 
 	bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);