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| author | Caesar Wang <wxt@rock-chips.com> | 2017-06-22 16:14:58 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-26 00:45:02 +0000 |
| commit | a0199d8e1a96d94828b31f77e0a29a282871a76a (patch) | |
| tree | de0547b24124e595108f7b18fbadabcd1f87b83e /src/soc/rockchip | |
| parent | d55f5ebe44ece4532ea28fe2c30a60bac8a7e81f (diff) | |
| download | coreboot-a0199d8e1a96d94828b31f77e0a29a282871a76a.tar.xz | |
rockchip/rk3399: update the ddr 200MHz frequency configuration
This patch updates the coreboot DDR Settings to match the configuration
used by ARM-Trusted-Firmware.
Change-Id: I34bc2950a9708ac89a5637bf682551e03d993fcc
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/rockchip')
| -rw-r--r-- | src/soc/rockchip/rk3399/clock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 35c96bcf37..980adf5000 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -636,7 +636,7 @@ void rkclk_configure_ddr(unsigned int hz) switch (hz) { case 200*MHz: dpll_cfg = (struct pll_div) - {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; + {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}; break; case 300*MHz: dpll_cfg = (struct pll_div) |