diff options
author | Julius Werner <jwerner@chromium.org> | 2015-02-19 14:51:15 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:22:28 +0200 |
commit | 2f37bd65518865688b9234afce0d467508d6f465 (patch) | |
tree | eba5ed799de966299602b30c70d51dd40eaadd73 /src/soc/samsung/exynos5250/i2c.c | |
parent | 1f60f971fc89ef841e81b978964b38278d597b1d (diff) | |
download | coreboot-2f37bd65518865688b9234afce0d467508d6f465.tar.xz |
arm(64): Globally replace writel(v, a) with write32(a, v)
This patch is a raw application of the following spatch to src/:
@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)
BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)
Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/samsung/exynos5250/i2c.c')
-rw-r--r-- | src/soc/samsung/exynos5250/i2c.c | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/src/soc/samsung/exynos5250/i2c.c b/src/soc/samsung/exynos5250/i2c.c index f92182a77a..e9eed406e5 100644 --- a/src/soc/samsung/exynos5250/i2c.c +++ b/src/soc/samsung/exynos5250/i2c.c @@ -117,34 +117,34 @@ static struct s3c24x0_i2c_bus i2c_busses[] = { static int i2c_int_pending(struct i2c_regs *regs) { - return readb(®s->con) & I2cConIntPending; + return read8(®s->con) & I2cConIntPending; } static void i2c_clear_int(struct i2c_regs *regs) { - writeb(readb(®s->con) & ~I2cConIntPending, ®s->con); + write8(®s->con, read8(®s->con) & ~I2cConIntPending); } static void i2c_ack_enable(struct i2c_regs *regs) { - writeb(readb(®s->con) | I2cConAckGen, ®s->con); + write8(®s->con, read8(®s->con) | I2cConAckGen); } static void i2c_ack_disable(struct i2c_regs *regs) { - writeb(readb(®s->con) & ~I2cConAckGen, ®s->con); + write8(®s->con, read8(®s->con) & ~I2cConAckGen); } static int i2c_got_ack(struct i2c_regs *regs) { - return !(readb(®s->stat) & I2cStatAck); + return !(read8(®s->stat) & I2cStatAck); } static int i2c_wait_for_idle(struct i2c_regs *regs) { int timeout = 1000 * 100; // 1s. while (timeout--) { - if (!(readb(®s->stat) & I2cStatBusy)) + if (!(read8(®s->stat) & I2cStatBusy)) return 0; udelay(10); } @@ -169,17 +169,17 @@ static int i2c_wait_for_int(struct i2c_regs *regs) static int i2c_send_stop(struct i2c_regs *regs) { - uint8_t mode = readb(®s->stat) & (I2cStatModeMask); - writeb(mode | I2cStatEnable, ®s->stat); + uint8_t mode = read8(®s->stat) & (I2cStatModeMask); + write8(®s->stat, mode | I2cStatEnable); i2c_clear_int(regs); return i2c_wait_for_idle(regs); } static int i2c_send_start(struct i2c_regs *regs, int read, int chip) { - writeb(chip << 1, ®s->ds); + write8(®s->ds, chip << 1); uint8_t mode = read ? I2cStatMasterRecv : I2cStatMasterXmit; - writeb(mode | I2cStatStartStop | I2cStatEnable, ®s->stat); + write8(®s->stat, mode | I2cStatStartStop | I2cStatEnable); i2c_clear_int(regs); if (i2c_wait_for_int(regs)) @@ -201,7 +201,7 @@ static int i2c_xmit_buf(struct i2c_regs *regs, uint8_t *data, int len) int i; for (i = 0; i < len; i++) { - writeb(data[i], ®s->ds); + write8(®s->ds, data[i]); i2c_clear_int(regs); if (i2c_wait_for_int(regs)) @@ -231,7 +231,7 @@ static int i2c_recv_buf(struct i2c_regs *regs, uint8_t *data, int len) if (i2c_wait_for_int(regs)) return 1; - data[i] = readb(®s->ds); + data[i] = read8(®s->ds); } return 0; @@ -246,7 +246,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int seg_count) if (!regs || i2c_wait_for_idle(regs)) return 1; - writeb(I2cStatMasterXmit | I2cStatEnable, ®s->stat); + write8(®s->stat, I2cStatMasterXmit | I2cStatEnable); int i; for (i = 0; i < seg_count; i++) { @@ -286,11 +286,11 @@ void i2c_init(unsigned bus, int speed, int slaveadd) // Set prescaler, divisor according to freq, also set ACKGEN, IRQ. val = (div & 0x0f) | 0xa0 | ((pres == 512) ? 0x40 : 0); - writel(val, &i2c->regs->con); + write32(&i2c->regs->con, val); // Init to SLAVE RECEIVE mode and clear I2CADDn. - writel(0, &i2c->regs->stat); - writel(slaveadd, &i2c->regs->add); + write32(&i2c->regs->stat, 0); + write32(&i2c->regs->add, slaveadd); // program Master Transmit (and implicit STOP). - writel(I2cStatMasterXmit | I2cStatEnable, &i2c->regs->stat); + write32(&i2c->regs->stat, I2cStatMasterXmit | I2cStatEnable); } |