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authorJulius Werner <jwerner@chromium.org>2015-02-19 20:19:23 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-21 08:22:40 +0200
commit941847652406982f3c9944fdd98cce4029b533fb (patch)
treeaf52ebeaa0245c9a3aa1e25c77f2271b67bff4a8 /src/soc/samsung/exynos5250
parent2f37bd65518865688b9234afce0d467508d6f465 (diff)
downloadcoreboot-941847652406982f3c9944fdd98cce4029b533fb.tar.xz
arm(64): Manually clean up the mess left by write32() transition
This patch is a manual cleanup of all the rubble left by coccinelle waltzing through our code base. It's generally not very good with line breaks and sometimes even eats comments, so this patch is my best attempt at putting it all back together. Also finally remove those hated writel()-style macros from the headers. BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: Id572f69c420c35577701feb154faa5aaf79cd13e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 817402a80ab77083728b55aed74b3b4202ba7f1d Original-Change-Id: I3b0dcd6fe09fc4e3b83ee491625d6dced98e3047 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254865 Reviewed-on: http://review.coreboot.org/9837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/samsung/exynos5250')
-rw-r--r--src/soc/samsung/exynos5250/clock_init.c4
-rw-r--r--src/soc/samsung/exynos5250/dmc_init_ddr3.c13
-rw-r--r--src/soc/samsung/exynos5250/usb.c43
3 files changed, 46 insertions, 14 deletions
diff --git a/src/soc/samsung/exynos5250/clock_init.c b/src/soc/samsung/exynos5250/clock_init.c
index 9cdd729f57..6f9614a0e6 100644
--- a/src/soc/samsung/exynos5250/clock_init.c
+++ b/src/soc/samsung/exynos5250/clock_init.c
@@ -224,8 +224,8 @@ void system_clock_init(struct mem_timings *mem,
;
if (mem->use_bpll) {
- write32(&exynos_clock->src_cdrex,
- MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL | MUX_MCLK_DPHY_SEL);
+ write32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK |
+ MUX_MCLK_CDREX_SEL | MUX_MCLK_DPHY_SEL);
} else {
write32(&exynos_clock->src_cdrex, CLK_REG_DISABLE);
}
diff --git a/src/soc/samsung/exynos5250/dmc_init_ddr3.c b/src/soc/samsung/exynos5250/dmc_init_ddr3.c
index 5a3cf3ef06..7bdbd6da14 100644
--- a/src/soc/samsung/exynos5250/dmc_init_ddr3.c
+++ b/src/soc/samsung/exynos5250/dmc_init_ddr3.c
@@ -86,8 +86,9 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
write32(&exynos_phy0_control->phy_con14, mem->phy0_pulld_dqs);
write32(&exynos_phy1_control->phy_con14, mem->phy1_pulld_dqs);
- write32(&exynos_dmc->concontrol,
- mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT));
+ write32(&exynos_dmc->concontrol, mem->concontrol |
+ (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) |
+ (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT));
update_reset_dll(exynos_dmc, DDR_MODE_DDR3);
@@ -137,7 +138,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
/* Power Down mode Configuration */
write32(&exynos_dmc->pwrdnconfig,
- mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT);
+ mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
+ mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT);
/* TimingRow, TimingData, TimingPower and Timingaref
* values as per Memory AC parameters
@@ -243,7 +245,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
write32(&exynos_dmc->memcontrol, mem->memcontrol);
/* Set DMC Concontrol and enable auto-refresh counter */
- write32(&exynos_dmc->concontrol,
- mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT));
+ write32(&exynos_dmc->concontrol, mem->concontrol |
+ (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) |
+ (mem->aref_en << CONCONTROL_AREF_EN_SHIFT));
return 0;
}
diff --git a/src/soc/samsung/exynos5250/usb.c b/src/soc/samsung/exynos5250/usb.c
index 3f6833657b..2dca58e553 100644
--- a/src/soc/samsung/exynos5250/usb.c
+++ b/src/soc/samsung/exynos5250/usb.c
@@ -52,12 +52,22 @@ static void setup_dwc3(struct exynos5_usb_drd_dwc3 *dwc3)
/* Set relevant registers to default values (clearing all reset bits) */
write32(&dwc3->usb3pipectl,
- 0x1 << 24 | 0x4 << 19 | 0x1 << 18 | 0x1 << 17 | 0x1 << 1 | 0);
+ 0x1 << 24 | /* activate PHY low power states */
+ 0x4 << 19 | /* low power delay value */
+ 0x1 << 18 | /* activate PHY low power delay */
+ 0x1 << 17 | /* enable SuperSpeed PHY suspend */
+ 0x1 << 1); /* default Tx deemphasis value */
/* Configure PHY clock turnaround for 8-bit UTMI+, disable suspend */
- write32(&dwc3->usb2phycfg, 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0);
-
- write32(&dwc3->ctl, 0x5dc << 19 | 0x1 << 16 | 0x1 << 12 | 0);
+ write32(&dwc3->usb2phycfg,
+ 0x9 << 10 | /* PHY clock turnaround for 8-bit UTMI+ */
+ 0x1 << 8 | /* enable PHY sleep in L1 */
+ 0x1 << 6); /* enable PHY suspend */
+
+ write32(&dwc3->ctl,
+ 0x5dc << 19 | /* suspend clock scale for 24MHz */
+ 0x1 << 16 | /* retry SS three times (bugfix from U-Boot) */
+ 0x1 << 12); /* port capability HOST */
}
void setup_usb_drd_dwc3()
@@ -77,13 +87,32 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy)
write32(&phy->utmi, 1 << 6);
write32(&phy->clkrst,
- 0x88 << 23 | 0x1 << 20 | 0x1 << 19 | 0x68 << 11 | 0x5 << 5 | 0x1 << 4 | 0x3 << 2 | 0x1 << 1 | 0x1 << 0 | 0);
+ 0x88 << 23 | /* spread spectrum refclk selector */
+ 0x1 << 20 | /* enable spread spectrum */
+ 0x1 << 19 | /* enable prescaler refclk */
+ 0x68 << 11 | /* multiplier for 24MHz refclk */
+ 0x5 << 5 | /* select 24MHz refclk (weird, from U-Boot) */
+ 0x1 << 4 | /* power supply in normal operating mode */
+ 0x3 << 2 | /* use external refclk (undocumented on 5420?)*/
+ 0x1 << 1 | /* force port reset */
+ 0x1 << 0); /* normal operating mode */
write32(&phy->param0,
- 0x9 << 26 | 0x3 << 22 | 0x1 << 20 | 0x1 << 18 | 0x3 << 13 | 0x3 << 9 | 0x3 << 6 | 0x4 << 3 | 0x4 << 0 | 0);
+ 0x9 << 26 | /* LOS level */
+ 0x3 << 22 | /* TX VREF tune */
+ 0x1 << 20 | /* TX rise tune */
+ 0x1 << 18 | /* TX res tune */
+ 0x3 << 13 | /* TX HS X Vtune */
+ 0x3 << 9 | /* TX FS/LS tune */
+ 0x3 << 6 | /* SQRX tune */
+ 0x4 << 3 | /* OTG tune */
+ 0x4 << 0); /* comp disc tune */
write32(&phy->param1,
- 0x7f << 19 | 0x7f << 12 | 0x20 << 6 | 0x1c << 0 | 0);
+ 0x7f << 19 | /* reserved */
+ 0x7f << 12 | /* Tx launch amplitude */
+ 0x20 << 6 | /* Tx deemphasis 6dB */
+ 0x1c << 0); /* Tx deemphasis 3.5dB (value from U-Boot) */
/* disable all test features */
write32(&phy->test, 0);