diff options
author | Julius Werner <jwerner@chromium.org> | 2015-02-19 14:51:15 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:22:28 +0200 |
commit | 2f37bd65518865688b9234afce0d467508d6f465 (patch) | |
tree | eba5ed799de966299602b30c70d51dd40eaadd73 /src/soc/samsung/exynos5420/i2c.c | |
parent | 1f60f971fc89ef841e81b978964b38278d597b1d (diff) | |
download | coreboot-2f37bd65518865688b9234afce0d467508d6f465.tar.xz |
arm(64): Globally replace writel(v, a) with write32(a, v)
This patch is a raw application of the following spatch to src/:
@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)
BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)
Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/samsung/exynos5420/i2c.c')
-rw-r--r-- | src/soc/samsung/exynos5420/i2c.c | 72 |
1 files changed, 36 insertions, 36 deletions
diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c index 28e3f0c331..1b541b7326 100644 --- a/src/soc/samsung/exynos5420/i2c.c +++ b/src/soc/samsung/exynos5420/i2c.c @@ -270,7 +270,7 @@ static int hsi2c_get_clk_details(struct i2c_bus *i2c, int *div, int *cycle, * temp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) * temp1 = (TSCLK_L + TSCLK_H + 2) */ - uint32_t flt_cycle = (readl(®s->i2c_conf) >> 16) & 0x7; + uint32_t flt_cycle = (read32(®s->i2c_conf) >> 16) & 0x7; int temp = (clkin / op_clk) - 8 - 2 * flt_cycle; // CLK_DIV max is 256. @@ -310,18 +310,18 @@ static void hsi2c_ch_init(struct i2c_bus *i2c, unsigned int frequency) uint32_t timing_sla = data_hd << 0; // Currently operating in fast speed mode. - writel(timing_fs1, ®s->i2c_timing_fs1); - writel(timing_fs2, ®s->i2c_timing_fs2); - writel(timing_fs3, ®s->i2c_timing_fs3); - writel(timing_sla, ®s->i2c_timing_sla); + write32(®s->i2c_timing_fs1, timing_fs1); + write32(®s->i2c_timing_fs2, timing_fs2); + write32(®s->i2c_timing_fs3, timing_fs3); + write32(®s->i2c_timing_sla, timing_sla); // Clear to enable timeout. - writel(readl(®s->i2c_timeout) & ~Hsi2cTimeoutEn, - ®s->i2c_timeout); + write32(®s->i2c_timeout, + read32(®s->i2c_timeout) & ~Hsi2cTimeoutEn); - writel(Hsi2cTrailingCount, ®s->usi_trailing_ctl); - writel(Hsi2cRxfifoEn | Hsi2cTxfifoEn, ®s->usi_fifo_ctl); - writel(readl(®s->i2c_conf) | Hsi2cAutoMode, ®s->i2c_conf); + write32(®s->usi_trailing_ctl, Hsi2cTrailingCount); + write32(®s->usi_fifo_ctl, Hsi2cRxfifoEn | Hsi2cTxfifoEn); + write32(®s->i2c_conf, read32(®s->i2c_conf) | Hsi2cAutoMode); } static void hsi2c_reset(struct i2c_bus *i2c) @@ -329,8 +329,8 @@ static void hsi2c_reset(struct i2c_bus *i2c) struct hsi2c_regs *regs = i2c->hsregs; // Set and clear the bit for reset. - writel(readl(®s->usi_ctl) | Hsi2cSwRst, ®s->usi_ctl); - writel(readl(®s->usi_ctl) & ~Hsi2cSwRst, ®s->usi_ctl); + write32(®s->usi_ctl, read32(®s->usi_ctl) | Hsi2cSwRst); + write32(®s->usi_ctl, read32(®s->usi_ctl) & ~Hsi2cSwRst); /* FIXME: This just assumes 100KHz as a default bus freq */ hsi2c_ch_init(i2c, 100000); @@ -356,13 +356,13 @@ static void i2c_ch_init(struct i2c_bus *i2c, int speed) // Set prescaler, divisor according to freq, also set ACKGEN, IRQ. val = (div & 0x0f) | 0xa0 | ((pres == 512) ? 0x40 : 0); - writel(val, ®s->con); + write32(®s->con, val); // Init to SLAVE RECEIVE mode and clear I2CADDn. - writel(0, ®s->stat); - writel(0, ®s->add); + write32(®s->stat, 0); + write32(®s->add, 0); // program Master Transmit (and implicit STOP). - writel(I2cStatMasterXmit | I2cStatEnable, ®s->stat); + write32(®s->stat, I2cStatMasterXmit | I2cStatEnable); } void i2c_init(unsigned bus, int speed, int slaveadd) @@ -430,7 +430,7 @@ static int hsi2c_senddata(struct hsi2c_regs *regs, const uint8_t *data, int len) { while (!hsi2c_check_transfer(regs) && len) { if (!(read32(®s->usi_fifo_stat) & Hsi2cTxFifoFull)) { - writel(*data++, ®s->usi_txdata); + write32(®s->usi_txdata, *data++); len--; } } @@ -452,7 +452,7 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop) { const uint32_t usi_ctl = Hsi2cFuncModeI2c | Hsi2cMaster; - writel(HSI2C_SLV_ADDR_MAS(seg->chip), ®s->i2c_addr); + write32(®s->i2c_addr, HSI2C_SLV_ADDR_MAS(seg->chip)); /* * We really only want to stop after this transaction (I think) if the @@ -465,14 +465,14 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop) seg->len | Hsi2cMasterRun | Hsi2cStopAfterTrans; if (seg->read) { - writel(usi_ctl | Hsi2cRxchon, ®s->usi_ctl); - writel(autoconf | Hsi2cReadWrite, ®s->i2c_auto_conf); + write32(®s->usi_ctl, usi_ctl | Hsi2cRxchon); + write32(®s->i2c_auto_conf, autoconf | Hsi2cReadWrite); if (hsi2c_recvdata(regs, seg->buf, seg->len)) return -1; } else { - writel(usi_ctl | Hsi2cTxchon, ®s->usi_ctl); - writel(autoconf, ®s->i2c_auto_conf); + write32(®s->usi_ctl, usi_ctl | Hsi2cTxchon); + write32(®s->i2c_auto_conf, autoconf); if (hsi2c_senddata(regs, seg->buf, seg->len)) return -1; @@ -481,7 +481,7 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop) if (hsi2c_wait_for_transfer(regs) != 1) return -1; - writel(Hsi2cFuncModeI2c, ®s->usi_ctl); + write32(®s->usi_ctl, Hsi2cFuncModeI2c); return 0; } @@ -510,34 +510,34 @@ static int hsi2c_transfer(struct i2c_bus *i2c, struct i2c_seg *segments, static int i2c_int_pending(struct i2c_regs *regs) { - return readb(®s->con) & I2cConIntPending; + return read8(®s->con) & I2cConIntPending; } static void i2c_clear_int(struct i2c_regs *regs) { - writeb(readb(®s->con) & ~I2cConIntPending, ®s->con); + write8(®s->con, read8(®s->con) & ~I2cConIntPending); } static void i2c_ack_enable(struct i2c_regs *regs) { - writeb(readb(®s->con) | I2cConAckGen, ®s->con); + write8(®s->con, read8(®s->con) | I2cConAckGen); } static void i2c_ack_disable(struct i2c_regs *regs) { - writeb(readb(®s->con) & ~I2cConAckGen, ®s->con); + write8(®s->con, read8(®s->con) & ~I2cConAckGen); } static int i2c_got_ack(struct i2c_regs *regs) { - return !(readb(®s->stat) & I2cStatAck); + return !(read8(®s->stat) & I2cStatAck); } static int i2c_wait_for_idle(struct i2c_regs *regs) { int timeout = 1000 * 100; // 1s. while (timeout--) { - if (!(readb(®s->stat) & I2cStatBusy)) + if (!(read8(®s->stat) & I2cStatBusy)) return 0; udelay(10); } @@ -562,17 +562,17 @@ static int i2c_wait_for_int(struct i2c_regs *regs) static int i2c_send_stop(struct i2c_regs *regs) { - uint8_t mode = readb(®s->stat) & (I2cStatModeMask); - writeb(mode | I2cStatEnable, ®s->stat); + uint8_t mode = read8(®s->stat) & (I2cStatModeMask); + write8(®s->stat, mode | I2cStatEnable); i2c_clear_int(regs); return i2c_wait_for_idle(regs); } static int i2c_send_start(struct i2c_regs *regs, int read, int chip) { - writeb(chip << 1, ®s->ds); + write8(®s->ds, chip << 1); uint8_t mode = read ? I2cStatMasterRecv : I2cStatMasterXmit; - writeb(mode | I2cStatStartStop | I2cStatEnable, ®s->stat); + write8(®s->stat, mode | I2cStatStartStop | I2cStatEnable); i2c_clear_int(regs); if (i2c_wait_for_int(regs)) @@ -594,7 +594,7 @@ static int i2c_xmit_buf(struct i2c_regs *regs, uint8_t *data, int len) int i; for (i = 0; i < len; i++) { - writeb(data[i], ®s->ds); + write8(®s->ds, data[i]); i2c_clear_int(regs); if (i2c_wait_for_int(regs)) @@ -624,7 +624,7 @@ static int i2c_recv_buf(struct i2c_regs *regs, uint8_t *data, int len) if (i2c_wait_for_int(regs)) return 1; - data[i] = readb(®s->ds); + data[i] = read8(®s->ds); } return 0; @@ -642,7 +642,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) if (!regs || i2c_wait_for_idle(regs)) return 1; - writeb(I2cStatMasterXmit | I2cStatEnable, ®s->stat); + write8(®s->stat, I2cStatMasterXmit | I2cStatEnable); int i; for (i = 0; i < count; i++) { |