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authorJulius Werner <jwerner@chromium.org>2019-12-02 22:03:27 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-12-04 14:11:17 +0000
commit55009af42c39f413c49503670ce9bc2858974962 (patch)
tree099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/samsung/exynos5420/usb.c
parent1c371572188a90ea16275460dd4ab6bf9966350b (diff)
downloadcoreboot-55009af42c39f413c49503670ce9bc2858974962.tar.xz
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/samsung/exynos5420/usb.c')
-rw-r--r--src/soc/samsung/exynos5420/usb.c50
1 files changed, 25 insertions, 25 deletions
diff --git a/src/soc/samsung/exynos5420/usb.c b/src/soc/samsung/exynos5420/usb.c
index 9dda4c100d..2f141c1b67 100644
--- a/src/soc/samsung/exynos5420/usb.c
+++ b/src/soc/samsung/exynos5420/usb.c
@@ -25,9 +25,9 @@
static void reset_dwc3(struct exynos5_usb_drd_dwc3 *dwc3)
{
- setbits_le32(&dwc3->ctl, 0x1 << 11); /* core soft reset */
- setbits_le32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */
- setbits_le32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */
+ setbits32(&dwc3->ctl, 0x1 << 11); /* core soft reset */
+ setbits32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */
+ setbits32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */
}
void reset_usb_drd0_dwc3()
@@ -89,7 +89,7 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy)
/* Set all PHY registers to default values */
/* XHCI Version 1.0, Frame Length adjustment 30 MHz */
- setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1);
+ setbits32(&phy->linksystem, 0x1 << 27 | 0x20 << 1);
/* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */
write32(&phy->utmi, 1 << 6);
@@ -132,20 +132,20 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy)
write32(&phy->resume, 0x0);
udelay(10);
- clrbits_le32(&phy->clkrst, 0x1 << 1); /* deassert port reset */
+ clrbits32(&phy->clkrst, 0x1 << 1); /* deassert port reset */
}
void setup_usb_drd0_phy()
{
printk(BIOS_DEBUG, "Powering up USB DRD0 PHY\n");
- setbits_le32(&exynos_power->usb_drd0_phy_ctrl, POWER_USB_PHY_CTRL_EN);
+ setbits32(&exynos_power->usb_drd0_phy_ctrl, POWER_USB_PHY_CTRL_EN);
setup_drd_phy(exynos_usb_drd0_phy);
}
void setup_usb_drd1_phy()
{
printk(BIOS_DEBUG, "Powering up USB DRD1 PHY\n");
- setbits_le32(&exynos_power->usb_drd1_phy_ctrl, POWER_USB_PHY_CTRL_EN);
+ setbits32(&exynos_power->usb_drd1_phy_ctrl, POWER_USB_PHY_CTRL_EN);
setup_drd_phy(exynos_usb_drd1_phy);
}
@@ -153,8 +153,8 @@ void setup_usb_host_phy(int hsic_gpio)
{
unsigned int hostphy_ctrl0;
- setbits_le32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN);
- setbits_le32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN);
+ setbits32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN);
+ setbits32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN);
printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n",
hsic_gpio ? "with" : "without");
@@ -175,17 +175,17 @@ void setup_usb_host_phy(int hsic_gpio)
HOST_CTRL0_UTMISWRST);
write32(&exynos_usb_host_phy->usbphyctrl0, hostphy_ctrl0);
udelay(10);
- clrbits_le32(&exynos_usb_host_phy->usbphyctrl0,
- HOST_CTRL0_LINKSWRST |
- HOST_CTRL0_UTMISWRST);
+ clrbits32(&exynos_usb_host_phy->usbphyctrl0,
+ HOST_CTRL0_LINKSWRST |
+ HOST_CTRL0_UTMISWRST);
udelay(20);
/* EHCI Ctrl setting */
- setbits_le32(&exynos_usb_host_phy->ehcictrl,
- EHCICTRL_ENAINCRXALIGN |
- EHCICTRL_ENAINCR4 |
- EHCICTRL_ENAINCR8 |
- EHCICTRL_ENAINCR16);
+ setbits32(&exynos_usb_host_phy->ehcictrl,
+ EHCICTRL_ENAINCRXALIGN |
+ EHCICTRL_ENAINCR4 |
+ EHCICTRL_ENAINCR8 |
+ EHCICTRL_ENAINCR16);
/* HSIC USB Hub initialization. */
if (hsic_gpio) {
@@ -194,15 +194,15 @@ void setup_usb_host_phy(int hsic_gpio)
gpio_direction_output(hsic_gpio, 1);
udelay(5000);
- clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
- HOST_CTRL0_SIDDQ |
- HOST_CTRL0_FORCESLEEP |
- HOST_CTRL0_FORCESUSPEND);
- setbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
- HOST_CTRL0_PHYSWRST);
+ clrbits32(&exynos_usb_host_phy->hsicphyctrl1,
+ HOST_CTRL0_SIDDQ |
+ HOST_CTRL0_FORCESLEEP |
+ HOST_CTRL0_FORCESUSPEND);
+ setbits32(&exynos_usb_host_phy->hsicphyctrl1,
+ HOST_CTRL0_PHYSWRST);
udelay(10);
- clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
- HOST_CTRL0_PHYSWRST);
+ clrbits32(&exynos_usb_host_phy->hsicphyctrl1,
+ HOST_CTRL0_PHYSWRST);
}
/* At this point we need to wait for 50ms before talking to