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authorJulius Werner <jwerner@chromium.org>2014-12-08 13:39:14 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-14 09:03:28 +0200
commit44cf870cb08b48dacdd6652baa15dba93fbc6216 (patch)
tree36a23e947289e3f7644dc4a65700bae177a59835 /src/soc/samsung/exynos5420
parentefcee767deed9d10628764eb9143724dd206d5fa (diff)
downloadcoreboot-44cf870cb08b48dacdd6652baa15dba93fbc6216.tar.xz
timer: Reestablish init_timer(), consolidate timer initialization calls
We have known for a while that the old x86 model of calling init_timer() in ramstage doesn't make sense on other archs (and is questionable in general), and finally removed it with CL:219719. However, now timer initialization is completely buried in the platform code, and it's hard to ensure it is done in time to set up timestamps. For three out of four non-x86 SoC vendors we have brought up for now, the timers need some kind of SoC-specific initialization. This patch reintroduces init_timer() as a weak function that can be overridden by platform code. The call in ramstage is restricted to x86 (and should probably eventually be removed from there as well), and other archs should call them at the earliest reasonable point in their bootblock. (Only changing arm for now since arm64 and mips bootblocks are still in very early state and should sync up to features in arm once their requirements are better understood.) This allows us to move timestamp_init() into arch code, so that we can rely on timestamps being available at a well-defined point and initialize our base value as early as possible. (Platforms who know that their timers start at zero can still safely call timestamp_init(0) again from platform code.) BRANCH=None BUG=None TEST=Booted Pinky, Blaze and Storm, compiled Daisy and Pit. Change-Id: I1b064ba3831c0c5b7965b1d88a6f4a590789c891 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ffaebcd3785c4ce998ac1536e9fdd46ce3f52bfa Original-Change-Id: Iece1614b7442d4fa9ca981010e1c8497bdea308d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234062 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9606 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/samsung/exynos5420')
-rw-r--r--src/soc/samsung/exynos5420/bootblock.c5
-rw-r--r--src/soc/samsung/exynos5420/include/soc/clk.h3
-rw-r--r--src/soc/samsung/exynos5420/timer.c5
3 files changed, 3 insertions, 10 deletions
diff --git a/src/soc/samsung/exynos5420/bootblock.c b/src/soc/samsung/exynos5420/bootblock.c
index f347677b94..59bc169204 100644
--- a/src/soc/samsung/exynos5420/bootblock.c
+++ b/src/soc/samsung/exynos5420/bootblock.c
@@ -30,11 +30,6 @@
void bootblock_soc_init(void)
{
- /* kick off the multi-core timer.
- * We want to do this as early as we can.
- */
- mct_start();
-
if (get_wakeup_state() == WAKEUP_DIRECT) {
wakeup();
/* Never returns. */
diff --git a/src/soc/samsung/exynos5420/include/soc/clk.h b/src/soc/samsung/exynos5420/include/soc/clk.h
index ca1d721f85..1677a9c18c 100644
--- a/src/soc/samsung/exynos5420/include/soc/clk.h
+++ b/src/soc/samsung/exynos5420/include/soc/clk.h
@@ -725,9 +725,6 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate);
/* Clock gate unused IP */
void clock_gate(void);
-void mct_start(void);
-uint64_t mct_raw_value(void);
-
/* These are the ratio's for configuring ARM clock */
struct arm_clk_ratios {
unsigned int arm_freq_mhz; /* Frequency of ARM core in MHz */
diff --git a/src/soc/samsung/exynos5420/timer.c b/src/soc/samsung/exynos5420/timer.c
index 0947d19d63..1e25771dbd 100644
--- a/src/soc/samsung/exynos5420/timer.c
+++ b/src/soc/samsung/exynos5420/timer.c
@@ -18,13 +18,14 @@
*/
#include <arch/io.h>
+#include <delay.h>
#include <soc/clk.h>
#include <stdint.h>
#include <timer.h>
static const uint32_t clocks_per_usec = MCT_HZ/1000000;
-uint64_t mct_raw_value(void)
+static uint64_t mct_raw_value(void)
{
uint64_t upper = readl(&exynos_mct->g_cnt_u);
uint64_t lower = readl(&exynos_mct->g_cnt_l);
@@ -32,7 +33,7 @@ uint64_t mct_raw_value(void)
return (upper << 32) | lower;
}
-void mct_start(void)
+void init_timer(void)
{
writel(readl(&exynos_mct->g_tcon) | (0x1 << 8),
&exynos_mct->g_tcon);