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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-17 10:56:26 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-23 15:52:09 +0000
commita342f3937e7ce159fd170ab8cd26ba799a3bc9e4 (patch)
tree4bd4540ba11286f465272c1fbee62dbf5f9789f8 /src/soc/samsung/exynos5420
parent9856892297ad997f586a1b4dd0a494f3764a0ce2 (diff)
downloadcoreboot-a342f3937e7ce159fd170ab8cd26ba799a3bc9e4.tar.xz
src: Remove unneeded whitespace
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/samsung/exynos5420')
-rw-r--r--src/soc/samsung/exynos5420/clock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c
index 3c4bb04794..04125d9cb1 100644
--- a/src/soc/samsung/exynos5420/clock.c
+++ b/src/soc/samsung/exynos5420/clock.c
@@ -582,7 +582,7 @@ int clock_epll_set_rate(unsigned long rate)
epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
/*
- * Required period ( in cycles) to generate a stable clock output.
+ * Required period (in cycles) to generate a stable clock output.
* The maximum clock time can be up to 3000 * PDIV cycles of PLLs
* frequency input (as per spec)
*/