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authorJulius Werner <jwerner@chromium.org>2019-10-02 17:28:56 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-12-02 22:12:10 +0000
commitbaf27dbaeb1f6791ebfc416f2175507686bd88ac (patch)
tree55c9d8224cde44d732b183624abf76b7446e418e /src/soc/samsung
parent4a1cbdd51aafa671ecb6c93a475ca9bf6f9ca914 (diff)
downloadcoreboot-baf27dbaeb1f6791ebfc416f2175507686bd88ac.tar.xz
cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/samsung')
-rw-r--r--src/soc/samsung/exynos5250/memlayout.ld3
-rw-r--r--src/soc/samsung/exynos5420/memlayout.ld3
2 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/samsung/exynos5250/memlayout.ld b/src/soc/samsung/exynos5250/memlayout.ld
index be4bb6edd7..eec9f60a91 100644
--- a/src/soc/samsung/exynos5250/memlayout.ld
+++ b/src/soc/samsung/exynos5250/memlayout.ld
@@ -18,7 +18,8 @@ SECTIONS
ROMSTAGE(0x2030000, 128K)
/* 32K hole */
TTB(0x2058000, 16K)
- PRERAM_CBFS_CACHE(0x205C000, 76K)
+ PRERAM_CBFS_CACHE(0x205C000, 68K)
+ CBFS_MCACHE(0x206D000, 8K)
FMAP_CACHE(0x206F000, 2K)
TPM_TCPA_LOG(0x206F800, 2K)
VBOOT2_WORK(0x2070000, 12K)
diff --git a/src/soc/samsung/exynos5420/memlayout.ld b/src/soc/samsung/exynos5420/memlayout.ld
index e29900110e..7c89413166 100644
--- a/src/soc/samsung/exynos5420/memlayout.ld
+++ b/src/soc/samsung/exynos5420/memlayout.ld
@@ -19,7 +19,8 @@ SECTIONS
ROMSTAGE(0x2030000, 128K)
/* 32K hole */
TTB(0x2058000, 16K)
- PRERAM_CBFS_CACHE(0x205C000, 74K)
+ PRERAM_CBFS_CACHE(0x205C000, 66K)
+ CBFS_MCACHE(0x206C800, 8K)
FMAP_CACHE(0x206E800, 2K)
STACK(0x206F000, 16K)
/* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't