diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-01-23 11:36:44 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-28 13:41:28 +0000 |
| commit | 251514d986ea9b978f4608d1994ca3307f1b51aa (patch) | |
| tree | 3f4018661bf96671baa7d8c192b609c8cf6dc212 /src/soc/samsung | |
| parent | 9e946079e82f1f2b7fbab498a9eec16d1fcd9216 (diff) | |
| download | coreboot-251514d986ea9b978f4608d1994ca3307f1b51aa.tar.xz | |
src: Don't use a #defines like Kconfig symbols
This is spotted using ./util/lint/kconfig_lint
To work around the issue, rename the prefix from `CONFIG_` to `CONF_`.
Change-Id: Ia31aed366bf768ab167ed5f8595bee8234aac46b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/samsung')
| -rw-r--r-- | src/soc/samsung/exynos5250/clock.c | 4 | ||||
| -rw-r--r-- | src/soc/samsung/exynos5420/clock.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c index a6cc3c78b9..7da7b74c53 100644 --- a/src/soc/samsung/exynos5250/clock.c +++ b/src/soc/samsung/exynos5250/clock.c @@ -22,7 +22,7 @@ #include <timer.h> /* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 +#define CONF_SYS_CLK_FREQ 24000000 static struct arm_clk_ratios arm_clk_ratios[] = { { @@ -213,7 +213,7 @@ unsigned long get_pll_clk(int pllreg) /* SDIV [2:0] */ s = r & 0x7; - freq = CONFIG_SYS_CLK_FREQ; + freq = CONF_SYS_CLK_FREQ; if (pllreg == EPLL) { k = k & 0xffff; diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index 0da35221ed..6d9258502d 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -22,7 +22,7 @@ #include <timer.h> /* input clock of PLL: SMDK5420 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 +#define CONF_SYS_CLK_FREQ 24000000 /* Epll Clock division values to achieve different frequency output */ static struct st_epll_con_val epll_div[] = { @@ -96,7 +96,7 @@ unsigned long get_pll_clk(int pllreg) /* SDIV [2:0] */ s = r & 0x7; - freq = CONFIG_SYS_CLK_FREQ; + freq = CONF_SYS_CLK_FREQ; if (pllreg == EPLL || pllreg == RPLL) { k = k & 0xffff; |