diff options
| author | Philipp Hug <philipp@hug.cx> | 2018-09-13 22:18:06 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2018-09-14 10:32:20 +0000 |
| commit | 91595724e7f302e0a876f0507e307f37f5871a7d (patch) | |
| tree | 47ce93e077716930744d92be13307e5b721c7715 /src/soc/sifive/fu540/sdram.c | |
| parent | 95c331b94b1d04ea34b480c83613c2141a02697e (diff) | |
| download | coreboot-91595724e7f302e0a876f0507e307f37f5871a7d.tar.xz | |
soc/sifive/fu540: Initialize SDRAM
Based on SiFive bootloader code
Change-Id: I71043ce9e458e25e64da28d53cd36b02d2e22acc
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28604
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/sifive/fu540/sdram.c')
| -rw-r--r-- | src/soc/sifive/fu540/sdram.c | 38 |
1 files changed, 37 insertions, 1 deletions
diff --git a/src/soc/sifive/fu540/sdram.c b/src/soc/sifive/fu540/sdram.c index 1ad36da2b3..6418b0d6e3 100644 --- a/src/soc/sifive/fu540/sdram.c +++ b/src/soc/sifive/fu540/sdram.c @@ -14,10 +14,46 @@ */ #include <soc/sdram.h> +#include <soc/addressmap.h> + +#include "regconfig-phy.h" +#include "regconfig-ctl.h" +#include "ux00ddr.h" + +#define DENALI_PHY_DATA ddr_phy_settings +#define DENALI_CTL_DATA ddr_ctl_settings +#include "ddrregs.h" + +#define DDR_SIZE (8UL * 1024UL * 1024UL * 1024UL) +#define DDRCTLPLL_F 55 +#define DDRCTLPLL_Q 2 void sdram_init(void) { - // TODO: implement + ux00ddr_writeregmap(FU540_DDRCTRL, ddr_ctl_settings, ddr_phy_settings); + ux00ddr_disableaxireadinterleave(FU540_DDRCTRL); + + ux00ddr_disableoptimalrmodw(FU540_DDRCTRL); + + ux00ddr_enablewriteleveling(FU540_DDRCTRL); + ux00ddr_enablereadleveling(FU540_DDRCTRL); + ux00ddr_enablereadlevelinggate(FU540_DDRCTRL); + if (ux00ddr_getdramclass(FU540_DDRCTRL) == DRAM_CLASS_DDR4) + ux00ddr_enablevreftraining(FU540_DDRCTRL); + + //mask off interrupts for leveling completion + ux00ddr_mask_leveling_completed_interrupt(FU540_DDRCTRL); + + ux00ddr_mask_mc_init_complete_interrupt(FU540_DDRCTRL); + ux00ddr_mask_outofrange_interrupts(FU540_DDRCTRL); + ux00ddr_setuprangeprotection(FU540_DDRCTRL, DDR_SIZE); + ux00ddr_mask_port_command_error_interrupt(FU540_DDRCTRL); + + const uint64_t ddr_size = DDR_SIZE; + const uint64_t ddr_end = FU540_DRAM + ddr_size; + ux00ddr_start(FU540_DDRCTRL, FU540_DDRBUSBLOCKER, ddr_end); + + ux00ddr_phy_fixup(FU540_DDRCTRL); } size_t sdram_size_mb(void) |