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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-09-21 17:34:50 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2018-09-26 18:52:27 +0000 |
| commit | 0fb58f32c48a5b7175b1597914bee33f87e377dc (patch) | |
| tree | 356128748a2ddf10c8a04ae29a85467f61fe938b /src/soc/sifive/fu540 | |
| parent | ae91cdabf60b97d3205de3aa55954dd4f5903845 (diff) | |
| download | coreboot-0fb58f32c48a5b7175b1597914bee33f87e377dc.tar.xz | |
soc/sifive/fu540: Remove PLL parameters from sdram.c
These parameters are not used and not necessary in sdram.c, because the
DDR PLL is configured in clock.c.
Change-Id: I8060bd21e05765cedf7bdabc28052c32774f9ca1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28710
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/sifive/fu540')
| -rw-r--r-- | src/soc/sifive/fu540/sdram.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/sifive/fu540/sdram.c b/src/soc/sifive/fu540/sdram.c index 6418b0d6e3..bf549bfa9f 100644 --- a/src/soc/sifive/fu540/sdram.c +++ b/src/soc/sifive/fu540/sdram.c @@ -25,8 +25,6 @@ #include "ddrregs.h" #define DDR_SIZE (8UL * 1024UL * 1024UL * 1024UL) -#define DDRCTLPLL_F 55 -#define DDRCTLPLL_Q 2 void sdram_init(void) { |