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authorPhilipp Hug <philipp@hug.cx>2018-09-13 18:11:56 +0200
committerRonald G. Minnich <rminnich@gmail.com>2018-09-14 09:28:06 +0000
commit199b75f58a0ffc2ad0871eb4853ca425c78b4893 (patch)
treefdd1d98ffa45c1e02372f5528f414008de498911 /src/soc/sifive/fu540
parent31dbfbc405ba7b26cacd2cfcaeff95e52d60ad99 (diff)
downloadcoreboot-199b75f58a0ffc2ad0871eb4853ca425c78b4893.tar.xz
arch/riscv: provide a monotonic timer
The RISC-V Privileged Architecture specification defines the Machine Time Registers (mtime and mtimecmp) in section 3.1.15. Makes it possible to use the generic udelay. The timer is enabled using RISCV_USE_ARCH_TIMER for the lowrisc, sifive and ucb soc. Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27434 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/sifive/fu540')
-rw-r--r--src/soc/sifive/fu540/Kconfig4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig
index 457d16bb4e..bee8292199 100644
--- a/src/soc/sifive/fu540/Kconfig
+++ b/src/soc/sifive/fu540/Kconfig
@@ -20,7 +20,11 @@ config SOC_SIFIVE_FU540
select ARCH_RAMSTAGE_RISCV
select BOOTBLOCK_CONSOLE
select DRIVERS_UART_SIFIVE
+ select GENERIC_UDELAY
+ select HAVE_MONOTONIC_TIMER
+ select RISCV_USE_ARCH_TIMER
select UART_OVERRIDE_REFCLK
+
if SOC_SIFIVE_FU540
config RISCV_ARCH