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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-09-20 16:55:33 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2018-09-26 18:52:54 +0000 |
| commit | 8ac6a19155b2e65dec83032e9b6ce9aa9a9e121b (patch) | |
| tree | 9896fd260289247479b4852f63175da07af80401 /src/soc/sifive/fu540 | |
| parent | 0fb58f32c48a5b7175b1597914bee33f87e377dc (diff) | |
| download | coreboot-8ac6a19155b2e65dec83032e9b6ce9aa9a9e121b.tar.xz | |
soc/sifive/fu540: Document #if ENV_ROMSTAGE line
Change-Id: Idcd72c558e46637b1b99e9613963436fedd4a8b9
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28699
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/sifive/fu540')
| -rw-r--r-- | src/soc/sifive/fu540/clock.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index eb7a8b5483..20dce23a64 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -121,8 +121,8 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI; // 33.33 Mhz after reset #define FU540_BASE_FQY 33330 +/* Clock initialization should only be done in romstage. */ #if ENV_ROMSTAGE - static void init_coreclk(void) { // switch coreclk to input reference frequency before modifying PLL @@ -240,8 +240,7 @@ void clock_init(void) for (int i = 0; i < 256; i++) asm volatile ("nop"); } - -#endif +#endif /* ENV_ROMSTAGE */ int clock_get_coreclk_khz(void) { |