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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-04-08 15:05:08 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-26 11:50:20 +0000 |
| commit | 93c9130a67c1e3d76d0c4fa2e6c9e2a2ee51a2f0 (patch) | |
| tree | cfecd0a6c3f26bf1ff82835e1248cb0488becae0 /src/soc/sifive/fu540 | |
| parent | 225b03534c81e2beb696f51175f14fd352f3090b (diff) | |
| download | coreboot-93c9130a67c1e3d76d0c4fa2e6c9e2a2ee51a2f0.tar.xz | |
arch/riscv: Store mprv bit in size_t
CSRs are XLEN bits wide (i.e. the same width as general purpose
registers), so size_t seems a little more correct than int.
This change doesn't affect functionality because MSTATUS_MPRV already
fits in 31 bits.
Change-Id: I003c1b88b4493681dc9b6178ac785be330203ef5
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/sifive/fu540')
0 files changed, 0 insertions, 0 deletions