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| author | Christian Walter <christian.walter@9elements.com> | 2020-09-30 13:44:02 +0200 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2020-10-09 16:25:11 +0000 |
| commit | 19df8d85e046849a8bdf4aebbd8dfbd774bea9ce (patch) | |
| tree | 698eefe22c6984530eb39289658960c06d06c9a9 /src/soc/sifive | |
| parent | 1c3fef2ca93dcdf2bca81a486fd3120476196760 (diff) | |
| download | coreboot-19df8d85e046849a8bdf4aebbd8dfbd774bea9ce.tar.xz | |
soc/intel/xeon_sp: Set CPU_ADDR_BITS to 46 for SKX and CPX
According to document number 338846 and 336062 this should be set to 46 bits.
Change-Id: I0bbe6c962ffc7d5dc722f1cacf55bc0d0615db59
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/soc/sifive')
0 files changed, 0 insertions, 0 deletions