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authorPhilipp Hug <philipp@hug.cx>2018-09-08 19:48:19 +0200
committerRonald G. Minnich <rminnich@gmail.com>2018-09-13 15:33:46 +0000
commit18764a328da0cf39ad83a658f9b84b99f220a30c (patch)
treea16fde14c64ad333ce9f21aa2fd2902c6cd01d1c /src/soc/sifive
parent7524400242be26610df143b5d1d781f875239c45 (diff)
downloadcoreboot-18764a328da0cf39ad83a658f9b84b99f220a30c.tar.xz
soc/sifive/fu540: Update clock settings according SiFive bootloader
The documentation unfortunately doesn't match what SiFive uses in their FSBL. Use the same values as in FSBL to make DDR RAM work. Change-Id: I844cc41ed197333adeae495e71ea70b4a9603650 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28582 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/sifive')
-rw-r--r--src/soc/sifive/fu540/clock.c38
1 files changed, 30 insertions, 8 deletions
diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c
index a59a1e8f9d..9b396a78a1 100644
--- a/src/soc/sifive/fu540/clock.c
+++ b/src/soc/sifive/fu540/clock.c
@@ -46,11 +46,13 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI;
#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15
#define PRCI_COREPLLCFG0_RANGE_SHIFT 18
#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
+#define PRCI_COREPLLCFG0_FSE_SHIFT 25
#define PRCI_COREPLLCFG0_DIVR_MASK (0x03f << PRCI_COREPLLCFG0_DIVR_SHIFT)
#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
#define PRCI_COREPLLCFG0_DIVQ_MASK (0x007 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
#define PRCI_COREPLLCFG0_RANGE_MASK (0x07 << PRCI_COREPLLCFG0_RANGE_SHIFT)
#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
+#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
#define PRCI_DDRPLLCFG0_LOCK (1u << 31)
#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
@@ -58,11 +60,13 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI;
#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18
#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24
+#define PRCI_DDRPLLCFG0_FSE_SHIFT 25
#define PRCI_DDRPLLCFG0_DIVR_MASK (0x03f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x007 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
#define PRCI_DDRPLLCFG0_RANGE_MASK (0x07 << PRCI_DDRPLLCFG0_RANGE_SHIFT)
#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
+#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)
#define PRCI_DDRPLLCFG1_MASK (1u << 31)
@@ -83,18 +87,30 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI;
#define PRCI_CORECLK_DIVF 59
#define PRCI_CORECLK_DIVQ 2
#define PRCI_CORECLK_RANGE 4
+#define PRCI_CORECLK_BYPASS 0
+#define PRCI_CORECLK_FSE 1
/*
* Section 7.4.3: DDR and Ethernet Subsystem Clocking and Reset
+ *
+ * Unfortunately the documentation example doesn't match the HiFive
+ * Unleashed board settings.
+ * Configuration values taken from SiFive FSBL:
+ * https://github.com/sifive/freedom-u540-c000-bootloader/blob/master/fsbl/main.c
+ *
+ * DDRPLL is set up for 933 MHz output frequency.
+ * divr = 0, divf = 55 (3730 MHz VCO), divq = 2
+ *
* GEMGXLPLL is set up for 125 MHz output frequency.
- * divr = 0, divf = 59 (4000 MHz VCO), divq = 5 DDRPLL is set up to run at the
- * memory MT/s divided by 4.
+ * divr = 0, divf = 59 (4000 MHz VCO), divq = 5
*/
#define PRCI_DDRCLK_DIVR 0
-#define PRCI_DDRCLK_DIVF 59
-#define PRCI_DDRCLK_DIVQ 5
+#define PRCI_DDRCLK_DIVF 55
+#define PRCI_DDRCLK_DIVQ 2
#define PRCI_DDRCLK_RANGE 4
+#define PRCI_DDRCLK_BYPASS 0
+#define PRCI_DDRCLK_FSE 1
// 33.33 Mhz after reset
#define FU540_BASE_FQY 33330
@@ -108,11 +124,14 @@ static void init_coreclk(void)
u32 c = read32(&prci->corepllcfg0);
clrsetbits_le32(&c, PRCI_COREPLLCFG0_DIVR_MASK
| PRCI_COREPLLCFG0_DIVF_MASK | PRCI_COREPLLCFG0_DIVQ_MASK
- | PRCI_COREPLLCFG0_RANGE_MASK | PRCI_COREPLLCFG0_BYPASS_MASK,
+ | PRCI_COREPLLCFG0_RANGE_MASK | PRCI_COREPLLCFG0_BYPASS_MASK
+ | PRCI_COREPLLCFG0_FSE_MASK,
(PRCI_CORECLK_DIVR << PRCI_COREPLLCFG0_DIVR_SHIFT)
| (PRCI_CORECLK_DIVF << PRCI_COREPLLCFG0_DIVF_SHIFT)
| (PRCI_CORECLK_DIVQ << PRCI_COREPLLCFG0_DIVQ_SHIFT)
- | (PRCI_CORECLK_RANGE << PRCI_COREPLLCFG0_RANGE_SHIFT));
+ | (PRCI_CORECLK_RANGE << PRCI_COREPLLCFG0_RANGE_SHIFT)
+ | (PRCI_CORECLK_BYPASS << PRCI_COREPLLCFG0_BYPASS_SHIFT)
+ | (PRCI_CORECLK_FSE << PRCI_COREPLLCFG0_FSE_SHIFT));
write32(&prci->corepllcfg0, c);
// wait for PLL lock
@@ -134,11 +153,14 @@ static void init_pll_ddr(void)
u32 c = read32(&prci->ddrpllcfg0);
clrsetbits_le32(&c, PRCI_DDRPLLCFG0_DIVR_MASK
| PRCI_DDRPLLCFG0_DIVF_MASK | PRCI_DDRPLLCFG0_DIVQ_MASK
- | PRCI_DDRPLLCFG0_RANGE_MASK | PRCI_DDRPLLCFG0_BYPASS_MASK,
+ | PRCI_DDRPLLCFG0_RANGE_MASK | PRCI_DDRPLLCFG0_BYPASS_MASK
+ | PRCI_DDRPLLCFG0_FSE_MASK,
(PRCI_DDRCLK_DIVR << PRCI_DDRPLLCFG0_DIVR_SHIFT)
| (PRCI_DDRCLK_DIVF << PRCI_DDRPLLCFG0_DIVF_SHIFT)
| (PRCI_DDRCLK_DIVQ << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
- | (PRCI_DDRCLK_RANGE << PRCI_DDRPLLCFG0_RANGE_SHIFT));
+ | (PRCI_DDRCLK_RANGE << PRCI_DDRPLLCFG0_RANGE_SHIFT)
+ | (PRCI_DDRCLK_BYPASS << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
+ | (PRCI_DDRCLK_FSE << PRCI_DDRPLLCFG0_FSE_SHIFT));
write32(&prci->ddrpllcfg0, c);
// wait for PLL lock