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authorJulius Werner <jwerner@chromium.org>2019-12-02 22:03:27 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-12-04 14:11:17 +0000
commit55009af42c39f413c49503670ce9bc2858974962 (patch)
tree099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/sifive
parent1c371572188a90ea16275460dd4ab6bf9966350b (diff)
downloadcoreboot-55009af42c39f413c49503670ce9bc2858974962.tar.xz
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/sifive')
-rw-r--r--src/soc/sifive/fu540/clock.c14
-rw-r--r--src/soc/sifive/fu540/spi.c2
2 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c
index 60a8a134c3..ef6221b262 100644
--- a/src/soc/sifive/fu540/clock.c
+++ b/src/soc/sifive/fu540/clock.c
@@ -84,7 +84,7 @@ static void configure_pll(u32 *reg, const struct pll_settings *s)
{
// Write the settings to the register
u32 c = read32(reg);
- clrsetbits_le32(&c, PRCI_PLLCFG_DIVR_MASK
+ clrsetbits32(&c, PRCI_PLLCFG_DIVR_MASK
| PRCI_PLLCFG_DIVF_MASK | PRCI_PLLCFG_DIVQ_MASK
| PRCI_PLLCFG_RANGE_MASK | PRCI_PLLCFG_BYPASS_MASK
| PRCI_PLLCFG_FSE_MASK,
@@ -155,13 +155,13 @@ static const struct pll_settings gemgxlpll_settings = {
static void init_coreclk(void)
{
// switch coreclk to input reference frequency before modifying PLL
- clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK,
+ clrsetbits32(&prci->coreclksel, PRCI_CORECLK_MASK,
PRCI_CORECLK_HFCLK);
configure_pll(&prci->corepllcfg0, &corepll_settings);
// switch coreclk to use corepll
- clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK,
+ clrsetbits32(&prci->coreclksel, PRCI_CORECLK_MASK,
PRCI_CORECLK_CORE_PLL);
}
@@ -169,25 +169,25 @@ static void init_pll_ddr(void)
{
// disable ddr clock output before reconfiguring the PLL
u32 cfg1 = read32(&prci->ddrpllcfg1);
- clrbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK);
+ clrbits32(&cfg1, PRCI_DDRPLLCFG1_MASK);
write32(&prci->ddrpllcfg1, cfg1);
configure_pll(&prci->ddrpllcfg0, &ddrpll_settings);
// enable ddr clock output
- setbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK);
+ setbits32(&cfg1, PRCI_DDRPLLCFG1_MASK);
write32(&prci->ddrpllcfg1, cfg1);
}
static void init_gemgxlclk(void)
{
u32 cfg1 = read32(&prci->gemgxlpllcfg1);
- clrbits_le32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK);
+ clrbits32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK);
write32(&prci->gemgxlpllcfg1, cfg1);
configure_pll(&prci->gemgxlpllcfg0, &gemgxlpll_settings);
- setbits_le32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK);
+ setbits32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK);
write32(&prci->gemgxlpllcfg1, cfg1);
}
diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c
index 5e30e77939..ae57cf6ef0 100644
--- a/src/soc/sifive/fu540/spi.c
+++ b/src/soc/sifive/fu540/spi.c
@@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/
-#include <arch/mmio.h>
+#include <device/mmio.h>
#include <soc/spi.h>
#include <soc/clock.h>
#include <soc/addressmap.h>