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authorJulius Werner <jwerner@chromium.org>2019-12-04 20:32:15 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-12-11 11:42:26 +0000
commit8245bd25a35466248c00bc7a4d0cf96f8391924a (patch)
tree5e3cc97038c161661fdaa0015ad37f1d73f4219c /src/soc/sifive
parentad27283a3c777f288254974cac233e47d1c0005d (diff)
downloadcoreboot-8245bd25a35466248c00bc7a4d0cf96f8391924a.tar.xz
fmap: Make FMAP_CACHE mandatory if it is configured in
Now that we have a CONFIG_NO_FMAP_CACHE to completely configure out the pre-RAM FMAP cache code, there's no point in allowing the region to be optional anymore. This patch makes the section required by the linker. If a board doesn't want to provide it, it has to select NO_FMAP_CACHE. Adding FMAP_CACHE regions to a couple more targets that I think can use them but I don't know anything about... please yell if one of these is a bad idea and I should mark them NO_FMAP_CACHE instead. Change-Id: Ic7d47772ab3abfa7e3a66815c3739d0af071abc2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/sifive')
-rw-r--r--src/soc/sifive/fu540/include/soc/memlayout.ld1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld
index df30ede510..46c559cba1 100644
--- a/src/soc/sifive/fu540/include/soc/memlayout.ld
+++ b/src/soc/sifive/fu540/include/soc/memlayout.ld
@@ -27,6 +27,7 @@ SECTIONS
BOOTBLOCK(FU540_L2LIM, 64K)
CAR_STACK(FU540_L2LIM + 64K, 20K)
PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K)
+ FMAP_CACHE(FU540_L2LIM + 92K, 2K)
ROMSTAGE(FU540_L2LIM + 128K, 128K)
PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K)
L2LIM_END(FU540_L2LIM + 2M)