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authorJulius Werner <jwerner@chromium.org>2019-10-02 17:28:56 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-12-02 22:12:10 +0000
commitbaf27dbaeb1f6791ebfc416f2175507686bd88ac (patch)
tree55c9d8224cde44d732b183624abf76b7446e418e /src/soc/ti
parent4a1cbdd51aafa671ecb6c93a475ca9bf6f9ca914 (diff)
downloadcoreboot-baf27dbaeb1f6791ebfc416f2175507686bd88ac.tar.xz
cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/ti')
-rw-r--r--src/soc/ti/am335x/memlayout.ld1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/ti/am335x/memlayout.ld b/src/soc/ti/am335x/memlayout.ld
index 720da26d6f..042febe7e5 100644
--- a/src/soc/ti/am335x/memlayout.ld
+++ b/src/soc/ti/am335x/memlayout.ld
@@ -9,6 +9,7 @@ SECTIONS
SRAM_START(0x402f0400)
BOOTBLOCK(0x402f0400, 20K)
FMAP_CACHE(0x402f0400+20K, 2K)
+ CBFS_MCACHE(0x402f0400+20K+2K, 8K)
TTB(0x402F8000, 16K)
ROMSTAGE(0x402F8000+16K, 40K)