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| author | Xiang Wang <wxjstz@126.com> | 2018-10-11 17:30:37 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-05 09:03:40 +0000 |
| commit | 7c9540ea1d46a776ec92b58f99074f51b430f9bb (patch) | |
| tree | dc9b3d25062791f40edd72ddcccaa3dd0171b85c /src/soc/ucb/riscv/Kconfig | |
| parent | c85f9c589726caba41970d5fbdadd8a147dd7956 (diff) | |
| download | coreboot-7c9540ea1d46a776ec92b58f99074f51b430f9bb.tar.xz | |
riscv: add support smp_pause / smp_resume
See https://doc.coreboot.org/arch/riscv/ we know that we need to execute
smp_pause at the start of each stage and smp_resume at the end of each
stage.
Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/29023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Diffstat (limited to 'src/soc/ucb/riscv/Kconfig')
| -rw-r--r-- | src/soc/ucb/riscv/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index 26adb56bfe..99b049068e 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -25,4 +25,8 @@ config RISCV_CODEMODEL string default "medany" +config RISCV_WORKING_HARTID + int + default 0 + endif |