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| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2017-02-10 21:36:58 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-14 17:53:20 +0100 |
| commit | b7fa7fbbd781cd075c06f44c49c93bead0b7f0e8 (patch) | |
| tree | 4a9d23e439bda3bc7f3e45a8d549730d2662b971 /src/soc/ucb/riscv | |
| parent | 0ff3b392a93edd6c785c8d40fa03034529e92429 (diff) | |
| download | coreboot-b7fa7fbbd781cd075c06f44c49c93bead0b7f0e8.tar.xz | |
soc/intel/skylake: Extract DIMM Information from FSP MEM INFO HOB
Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB
and save it in CBMEM.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS Table from Kernel command "dmidecode".
Change-Id: I593d4ccb0d4866e99913a73c49b2f000b51827d1
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18275
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/ucb/riscv')
0 files changed, 0 insertions, 0 deletions