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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-01-14 19:51:47 +0100 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-01-27 01:41:40 +0100 |
| commit | 77b1655d9bccd0c93cb1a6b86ecc98e2074504a3 (patch) | |
| tree | 4a5dc149e9860c6755499053e2729c6937ccf24f /src/soc/ucb/riscv | |
| parent | 40ce5d90b8b2f2b90e7198ab64e507a59bed93c7 (diff) | |
| download | coreboot-77b1655d9bccd0c93cb1a6b86ecc98e2074504a3.tar.xz | |
vboot2: add verstage
This reverts the revert commit 5780d6f3876723b94fbe3653c9d87dad6330862e
and fixes the build issue that cuased it to be reverted.
Verstage will host vboot2 for firmware verification.
It's a stage in the sense that it has its own set of toolchains,
compiler flags,
and includes. This allows us to easily add object files as needed. But
it's directly linked to bootblock. This allows us to avoid code
duplication for stage loading and jumping (e.g. cbfs driver) for the
boards
where bootblock has to run in a different architecture (e.g. Tegra124).
To avoid name space conflict, verstage symbols are prefixed with
verstage_.
TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze.
BUG=None
BRANCH=none
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac
Original-Reviewed-on: https://chromium-review.googlesource.com/204376
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2a83b87c29d98d97ae316091cf3ed7b024e21daf
Reviewed-on: http://review.coreboot.org/8224
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/ucb/riscv')
| -rw-r--r-- | src/soc/ucb/riscv/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index be4a675cd6..e38ac29b0b 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -1,6 +1,7 @@ config SOC_UCB_RISCV select ARCH_RISCV select ARCH_BOOTBLOCK_RISCV + select ARCH_VERSTAGE_RISCV select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV select DYNAMIC_CBMEM |