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authorPhilipp Hug <philipp@hug.cx>2019-02-06 06:48:51 +0100
committerron minnich <rminnich@gmail.com>2019-02-13 04:49:14 +0000
commitb09e5001f3071e82ccf7ec64c9cf9a4768d660b1 (patch)
treef1a673efd5da4bcd24886b7c049335f52b8c1c75 /src/soc/ucb/riscv
parent540a66404591ef41e2581df01647e5788ef0c808 (diff)
downloadcoreboot-b09e5001f3071e82ccf7ec64c9cf9a4768d660b1.tar.xz
riscv: Add initial support for 32bit boards
* Adding separate targets for 32bit and 64bit qemu * Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv * rv32/rv64 is currently configured with ARCH_RISCV_RV32/RV64 and not per stage. This should probably be changed later. TEST=Boots to "Payload not loaded." on 32bit qemu using the following commands: util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf qemu-system-riscv32 -M virt -m 1024M -nographic -kernel build/coreboot.elf Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/31253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/ucb/riscv')
-rw-r--r--src/soc/ucb/riscv/Kconfig21
1 files changed, 20 insertions, 1 deletions
diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig
index aa352d932b..ad48c1cb76 100644
--- a/src/soc/ucb/riscv/Kconfig
+++ b/src/soc/ucb/riscv/Kconfig
@@ -1,5 +1,4 @@
config SOC_UCB_RISCV
- select ARCH_RISCV_RV64
select ARCH_RISCV_S
select ARCH_RISCV_U
select ARCH_RISCV_PMP
@@ -15,6 +14,8 @@ config SOC_UCB_RISCV
if SOC_UCB_RISCV
+if ARCH_RISCV_RV64
+
config RISCV_ARCH
string
default "rv64imafd"
@@ -27,6 +28,24 @@ config RISCV_CODEMODEL
string
default "medany"
+endif
+
+if ARCH_RISCV_RV32
+
+config RISCV_ARCH
+ string
+ default "rv32im"
+
+config RISCV_ABI
+ string
+ default "ilp32"
+
+config RISCV_CODEMODEL
+ string
+ default "medany"
+
+endif
+
config RISCV_WORKING_HARTID
int
default 0