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author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2017-11-20 00:57:32 +0100 |
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committer | Martin Roth <martinroth@google.com> | 2017-12-02 05:24:32 +0000 |
commit | 3ca8b598ed4ea16fd55d0d8108749c1da537a036 (patch) | |
tree | 36f54ae9d8b69088e60c51331ca02d98b0b96ece /src/soc/ucb/riscv | |
parent | b0de851ebb032bd1517790b1c07d408d84e82f94 (diff) | |
download | coreboot-3ca8b598ed4ea16fd55d0d8108749c1da537a036.tar.xz |
arch/riscv: Remove the current SBI implementation
This Supervisor Binary Interface, which is based on a page of code
that's provided to operating systems by the M-mode software, has been
superseded by a different (currently not really documented) SBI, which
is based on directly executing ECALLs instructions. Thus some of our
code becomes obsolete. Just rip it out until we implement the new SBI.
Change-Id: Iec9c20b750f39a2b8f1553e25865bbf150605a6d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/ucb/riscv')
0 files changed, 0 insertions, 0 deletions