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authorChris Wang <chris.wang@amd-corp-partner.google.com>2020-05-19 14:46:35 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-07-06 06:14:07 +0000
commit04dfc26f94b7682aafc95621806a79ab541c92b5 (patch)
tree1d12e3d146d2be2f2622935bb3fdcb932401d3e9 /src/soc
parent6e62223f01bedd20628845f2c2dd0371715aa4aa (diff)
downloadcoreboot-04dfc26f94b7682aafc95621806a79ab541c92b5.tar.xz
mb/google/zork: Add USB2 phy tuning parameter for SI tuning
Add the USB2 phy tuning parameter to adjust the USB 2.0 PHY driving strength. BUG=b:156315391 TEST=Build, verified the tuning value been applied on Trembyle. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I3d31792d26729e0acb044282c5300886663dde51 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2208524 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Tested-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/picasso/chip.h32
-rw-r--r--src/soc/amd/picasso/fsp_params.c9
2 files changed, 41 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index f11f800787..1dbe3d9dd4 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -14,6 +14,30 @@
#include <acpi/acpi_device.h>
#include <arch/smp/mpspec.h>
+/*
+ USB 2.0 PHY Parameters
+*/
+struct usb2_phy_tune {
+ /* Disconnect Threshold Adjustment. Range 0 - 0x7 */
+ uint8_t com_pds_tune;
+ /* Squelch Threshold Adjustment. Range 0 - 0x7 */
+ uint8_t sq_rx_tune;
+ /* FS/LS Source Impedance Adjustment. Range 0 - 0xF */
+ uint8_t tx_fsls_tune;
+ /* HS Transmitter Pre-Emphasis Curent Control. Range 0 - 0x3 */
+ uint8_t tx_pre_emp_amp_tune;
+ /* HS Transmitter Pre-Emphasis Duration Control. Range: 0 - 0x1 */
+ uint8_t tx_pre_emp_pulse_tune;
+ /* HS Transmitter Rise/Fall Time Adjustment. Range: 0 - 0x3 */
+ uint8_t tx_rise_tune;
+ /* HS DC Voltage Level Adjustment. Range 0 - 0xF */
+ uint8_t rx_vref_tune;
+ /* Transmitter High-Speed Crossover Adjustment. Range 0 - 0x3 */
+ uint8_t tx_hsxv_tune;
+ /* USB Source Impedance Adjustment. Range 0 - 0x3. */
+ uint8_t tx_res_tune;
+};
+
struct soc_amd_picasso_config {
struct soc_amd_common_config common_config;
/*
@@ -108,6 +132,14 @@ struct soc_amd_picasso_config {
} sd_emmc_config;
uint8_t xhci0_force_gen1;
+
+ struct usb2_phy_tune usb_2_port_0_tune_params;
+ struct usb2_phy_tune usb_2_port_1_tune_params;
+ struct usb2_phy_tune usb_2_port_2_tune_params;
+ struct usb2_phy_tune usb_2_port_3_tune_params;
+ struct usb2_phy_tune usb_2_port_4_tune_params;
+ struct usb2_phy_tune usb_2_port_5_tune_params;
+
};
typedef struct soc_amd_picasso_config config_t;
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index 9decbbf57b..10bca005e7 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -98,7 +98,16 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg)
static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg,
const struct soc_amd_picasso_config *cfg)
{
+ size_t num = sizeof(struct usb2_phy_tune);
+
scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1;
+
+ memcpy(scfg->fch_usb_2_port0_phy_tune, &cfg->usb_2_port_0_tune_params, num);
+ memcpy(scfg->fch_usb_2_port1_phy_tune, &cfg->usb_2_port_1_tune_params, num);
+ memcpy(scfg->fch_usb_2_port2_phy_tune, &cfg->usb_2_port_2_tune_params, num);
+ memcpy(scfg->fch_usb_2_port3_phy_tune, &cfg->usb_2_port_3_tune_params, num);
+ memcpy(scfg->fch_usb_2_port4_phy_tune, &cfg->usb_2_port_4_tune_params, num);
+ memcpy(scfg->fch_usb_2_port5_phy_tune, &cfg->usb_2_port_5_tune_params, num);
}
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)