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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-11-13 10:03:31 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-19 08:17:06 +0000 |
| commit | 0ce41f1a116a816e774ebbd1130d27d7ee70e7e9 (patch) | |
| tree | 983a793e01bbf09ed1e9c74534d4b78f9d3f2866 /src/soc | |
| parent | 16f9bf83e00c786275d3fcc9d512d145ef6c93c9 (diff) | |
| download | coreboot-0ce41f1a116a816e774ebbd1130d27d7ee70e7e9.tar.xz | |
src: Add required space after "switch"
Change-Id: I85cf93e30606bc7838852bd300a369e79370629a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage_fsp20.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index eed9d8bef0..2a601588d6 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -101,7 +101,7 @@ static void save_dimm_info(void) if (src_dimm->Status != DIMM_PRESENT) continue; - switch(memory_info_hob->MemoryType) { + switch (memory_info_hob->MemoryType) { case MRC_DDR_TYPE_DDR4: ddr_type = MEMORY_TYPE_DDR4; break; |