diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-02-11 11:06:19 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-02-16 08:42:08 +0100 |
| commit | 0de80da24cc39003f61f86452f46c9b48c95ae4d (patch) | |
| tree | 05dc491b12f44adc9a31a3b7d027fc32045d54a7 /src/soc | |
| parent | 4e084796886259133d9226c40822e44599a41302 (diff) | |
| download | coreboot-0de80da24cc39003f61f86452f46c9b48c95ae4d.tar.xz | |
soc/intel/skylake: Add support for SPI device
Add a new PCI driver for SPI devices with supported PCI ids. Also,
provide a translation table to convert struct device structure into SPI
bus number.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: If860eb819f2ce5ae5443f808b356af57f86c52be
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18341
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pci_devs.h | 10 | ||||
| -rw-r--r-- | src/soc/intel/skylake/spi.c | 37 |
2 files changed, 47 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 974f1d8e19..a19a7c6007 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -176,4 +176,14 @@ static inline int i2c_devfn_to_bus(unsigned devfn) return -1; } +static inline int spi_devfn_to_bus(unsigned devfn) +{ + switch (devfn) { + case PCH_DEVFN_SPI: return 0; + case PCH_DEVFN_GSPI0: return 1; + case PCH_DEVFN_GSPI1: return 2; + } + return -1; +} + #endif diff --git a/src/soc/intel/skylake/spi.c b/src/soc/intel/skylake/spi.c index ddff4dcbcd..4a2ae9d8b8 100644 --- a/src/soc/intel/skylake/spi.c +++ b/src/soc/intel/skylake/spi.c @@ -15,6 +15,12 @@ */ #include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/spi.h> +#include <soc/ramstage.h> #include <spi-generic.h> /* SPI controller managing the flash-device SPI. */ @@ -61,3 +67,34 @@ const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { }; const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); + +#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) + +static int spi_dev_to_bus(struct device *dev) +{ + return spi_devfn_to_bus(dev->path.pci.devfn); +} + +static struct spi_bus_operations spi_bus_ops = { + .dev_to_bus = &spi_dev_to_bus, +}; + +static struct device_operations spi_dev_ops = { + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .scan_bus = &scan_generic_bus, + .ops_pci = &soc_pci_ops, + .ops_spi_bus = &spi_bus_ops, +}; + +static const unsigned short pci_device_ids[] = { + 0x9d24, 0x9d29, 0x9d2a, 0 +}; + +static const struct pci_driver pch_spi __pci_driver = { + .ops = &spi_dev_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; +#endif |