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| author | John Zhao <john.zhao@intel.com> | 2020-03-31 21:55:35 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-14 10:09:27 +0000 |
| commit | 17277ff6580e054eb7ac33f46c3c58c4bee9e886 (patch) | |
| tree | 46893fe77d917362641b89be32de9751c8f032f0 /src/soc | |
| parent | 72d93667212b0315a323b073d2f6334462377d2c (diff) | |
| download | coreboot-17277ff6580e054eb7ac33f46c3c58c4bee9e886.tar.xz | |
soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type
TCSS TBT PCIE root ports scope type was mistakenly set to PCI_ENDPOINT.
Fix the scope type to be PCI_SUB.
BUG=b:141609884
TEST=Booted to kernel and verified no TBT PCIE root ports scope
type mismatch error in kernel log.
Change-Id: I844e7e9583992be496223fb51f24c5aa24fc7d21
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 9e7ff56752..36c488b575 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -235,7 +235,7 @@ static unsigned long soc_fill_dmar(unsigned long current) unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); - current += acpi_create_dmar_ds_pci(current, 0, 7, i); + current += acpi_create_dmar_ds_pci_br(current, 0, 7, i); acpi_dmar_drhd_fixup(tmp, current); } |