summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2017-07-04 15:56:41 +0530
committerDuncan Laurie <dlaurie@chromium.org>2017-07-12 04:00:13 +0000
commit1914337936dde751fe43735a62b7222861f7fcec (patch)
treeb42debf3dc1c84859297285b544b90529fc69912 /src/soc
parentfa2786a01008588f0effb92874e776c668c63b22 (diff)
downloadcoreboot-1914337936dde751fe43735a62b7222861f7fcec.tar.xz
soc/intel/skylake: Perform PCR read after all PCR write
BIOS must ensure to read same PCR offset after PCR write operation is done. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<->D3 transition on eve failing unit. No hard hang with this fix. Change-Id: Id3d567aab517b16ff99a526fc29c2d71bf4042d0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/skylake/acpi/pcr.asl16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/acpi/pcr.asl b/src/soc/intel/skylake/acpi/pcr.asl
index 4b8576b804..c73830fe46 100644
--- a/src/soc/intel/skylake/acpi/pcr.asl
+++ b/src/soc/intel/skylake/acpi/pcr.asl
@@ -53,6 +53,14 @@ Method (PCRA, 3, Serialized)
DATA, 32
}
And (DATA, Arg2, DATA)
+
+ /*
+ * After every write one needs to read an innocuous register
+ * to ensure the writes are completed for certain ports. This is done
+ * for all ports so that the callers don't need the per-port knowledge
+ * for each transaction.
+ */
+ PCRR (Arg0, Arg1)
}
/*
@@ -69,4 +77,12 @@ Method (PCRO, 3, Serialized)
DATA, 32
}
Or (DATA, Arg2, DATA)
+
+ /*
+ * After every write one needs to read an innocuous register
+ * to ensure the writes are completed for certain ports. This is done
+ * for all ports so that the callers don't need the per-port knowledge
+ * for each transaction.
+ */
+ PCRR (Arg0, Arg1)
}