diff options
| author | Julius Werner <jwerner@chromium.org> | 2014-11-24 13:50:46 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-15 16:27:23 +0200 |
| commit | 2460a5564f9a5c3c30922a5faba080cedc7b726f (patch) | |
| tree | 961557018fafd8bdbf67b7e40758f2fa5cb06f6b /src/soc | |
| parent | 5984aad9c8a0fad5b20db7d03832d3b3510bcfd6 (diff) | |
| download | coreboot-2460a5564f9a5c3c30922a5faba080cedc7b726f.tar.xz | |
veyron: Trigger hard reset (via GPIO) if last reboot was caused by watchdog
Like Nyan, Veyron boards use a GPIO to reset the system so that we can
make the accompanying TPM reset secure and unforgeable. The normal
kernel reboot driver knows that, but the SoC-internal watchdog doesn't.
This patch implements a check for the global reset status register in
the early bootblock and triggers a hard_reset() when it matches "first
global watchdog reset" or "second global watchdog reset". Seems that
the difference between the two is is a choice controlled by
wdt_glb_srst_ctrl (unconfirmed), and we want this code to run in both
cases.
BRANCH=None
BUG=chrome-os-partner:33141
TEST=Run 'mem w 0xff800000 0x9' from the command line, watch how you end
up in recovery without this patch but can boot normally with it.
Change-Id: Ice79648831e1e97d22325711da9e82bbf6bf3c75
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 5d7cb52b2c2dcb2fff0bf83fc168439dade4b1b7
Original-Change-Id: I2581bde84f0445c15896060544e9acb60de91c8c
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/231734
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9629
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/rockchip/rk3288/clock.c | 6 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/include/soc/clock.h | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index fe42910dde..ab12e8c896 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -640,3 +640,9 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz) } return 0; } + +int rkclk_was_watchdog_reset(void) +{ + /* Bits 5 and 4 are "second" and "first" global watchdog reset. */ + return readl(&cru_ptr->cru_glb_rst_st) & 0x30; +} diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h index b8f892bbed..cbf4ba0df3 100644 --- a/src/soc/rockchip/rk3288/include/soc/clock.h +++ b/src/soc/rockchip/rk3288/include/soc/clock.h @@ -49,4 +49,5 @@ void rkclk_configure_tsadc(unsigned int hz); void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz); int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz); void rkclk_configure_edp(void); +int rkclk_was_watchdog_reset(void); #endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */ |