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authorAngel Pons <th3fanbus@gmail.com>2020-12-11 16:48:39 +0100
committerHung-Te Lin <hungte@chromium.org>2020-12-14 08:18:22 +0000
commit24787ffe306fed78e295085102758f784e5be3d9 (patch)
tree20f9e62139a5dae35664fdb9ff4549f61ec9f28e /src/soc
parentd3713fdb484275fd8f97fe70dc2d2a0d374a9953 (diff)
downloadcoreboot-24787ffe306fed78e295085102758f784e5be3d9.tar.xz
soc/intel/elkhartlake: Drop unreferenced devicetree settings
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: Ia928c4bbddd1c160228a9af8faf5d4be787f73f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/elkhartlake/chip.h8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index 7cd29b4f40..37237bbbc1 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -132,17 +132,9 @@ struct soc_intel_elkhartlake_config {
/* Enable if SD Card Power Enable Signal is Active High */
uint8_t SdCardPowerEnableActiveHigh;
- /* Integrated Sensor */
- uint8_t PchIshEnable;
-
- /* Heci related */
- uint8_t Heci3Enabled;
-
/* Gfx related */
- uint8_t IgdDvmt50PreAlloc;
uint8_t SkipExtGfxScan;
- uint32_t GraphicsConfigPtr;
uint8_t Device4Enable;
/* HeciEnabled decides the state of Heci1 at end of boot